Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

set_disable_clockgating_check constraint in SDC during synthesis stage

Status
Not open for further replies.

howardzhou123

Newbie level 1
Joined
Feb 20, 2018
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
10
How to enable and disable the clock gating check in SDC, as set_disable_clockgating_check need
know the instance name which need later stage, how to set this contraint during Synthesis stage
while still have RTL code.
what is the best way to do that, my design have a lot unwanted AND,NAND,NOR,AOI combinational
clockgating check, I have do a lot of manual work to disable unwanted clock gating check, want it do in early stage like RTL stage.? any comments
 

You can't do it at RTL stage since clock gating is not there yet.

I also don't understand what the problem is here. Are you sure you want to ignore all clock gating paths? Why?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top