howardzhou123
Newbie level 1
How to enable and disable the clock gating check in SDC, as set_disable_clockgating_check need
know the instance name which need later stage, how to set this contraint during Synthesis stage
while still have RTL code.
what is the best way to do that, my design have a lot unwanted AND,NAND,NOR,AOI combinational
clockgating check, I have do a lot of manual work to disable unwanted clock gating check, want it do in early stage like RTL stage.? any comments
know the instance name which need later stage, how to set this contraint during Synthesis stage
while still have RTL code.
what is the best way to do that, my design have a lot unwanted AND,NAND,NOR,AOI combinational
clockgating check, I have do a lot of manual work to disable unwanted clock gating check, want it do in early stage like RTL stage.? any comments