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IC Compiler error for clock tree synthesis

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dayana42200

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Hi all.

Based on the log report below, I dont unserstand why there is error during clock tree synthesis?
Code:
icc_shell> clock_opt
Warning: Starting from the 2011.09-SP4 release, clock_opt will NOT perform congestion-driven placement by default. (PSYN-1111)

The options for clock_opt:
--------------------------
COPT:  Clock Tree Synthesis                 : Yes
COPT:  Post CTS Optimization                : Yes
COPT:  Concurrent Clock/Data Optimization   : No
COPT:  Operation Condition                  : max
COPT:  Balance Inter Clock Delay            : No
COPT:  Route Clock Nets                     : Yes
COPT:  Update Clock Latency                 : No
COPT:  Optimize Hold for All Clocks         : No
COPT:  Optimize Hold Timing Only            : No
COPT:  Optimize DFT                         : No
COPT:  Area Recovery                        : No
COPT:  Size Only                            : No
COPT:  In Place Size Only                   : No
COPT:  Congestion removal                   : No
COPT:  Optimize Power                       : No
---------------------------------------------------

Executing ICC clock_opt...
medium
*
Building clock tree...
Operating Condition is max
Information: There is no scenario with cts_mode set to true, CTS will use old cts_scenario flow. (CTS-1115)
CTS Operating Condition(s): MAX(Worst) 

  Loading design 'Sync_Rst_CompTop'




Information: Library Manufacturing Grid(GridResolution) : 5
Information: Time Unit from Milkyway design library: 'ns' 
Information: Design Library and main library timing units are matched - 1.000 ns. 
Information: Resistance Unit from Milkyway design library: 'kohm' 
Information: Design Library and main library resistance units are matched - 1.000 kohm. 
Information: Capacitance Unit from Milkyway design library: 'pf' 
Information: Design Library and main library capacitance units are matched - 1.000 pf. 
[begin initializing data for legality checker]

Initializing Data Structure ...
INFO: legalizer_via_spacing_check_mode 0
  Reading technology information ...
    Technology table contains 6 routable metal layers
    This is considered as a 6-metal-layer design
    Reading library information from DB ...
  Reading misc information ...
    array <unit> has 0 vertical and 8 horizontal rows
    8 pre-routes for placement blockage/checking
    15 pre-routes for map congestion calculation
  Checking information read in ...
    design style = Horizontal masters, Horizontal rows

  Preprocessing design ...
    splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
Setting the GR Options
****************************************************************
Information: TLUPlus based RC computation is enabled. (RCEX-141)
****************************************************************
Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007)
Information: The RC model used is TLU+. (RCEX-015)
Information: Library Derived Cap for layer METAL : 1.9e-07 1.9e-07 (RCEX-011)
Information: Library Derived Res for layer METAL : 0.00065 0.00035 (RCEX-011)
Information: Library Derived Cap for layer METAL2 : 2.4e-07 2.4e-07 (RCEX-011)
Information: Library Derived Res for layer METAL2 : 0.00039 0.0002 (RCEX-011)
Information: Library Derived Cap for layer METAL3 : 2.4e-07 2.4e-07 (RCEX-011)
Information: Library Derived Res for layer METAL3 : 0.00039 0.0002 (RCEX-011)
Information: Library Derived Cap for layer METAL4 : 2e-07 1.9e-07 (RCEX-011)
Information: Library Derived Res for layer METAL4 : 0.00039 0.0002 (RCEX-011)
Information: Library Derived Cap for layer METAL5 : 2e-07 2e-07 (RCEX-011)
Information: Library Derived Res for layer METAL5 : 0.00019 0.0001 (RCEX-011)
Information: Library Derived Cap for layer METAL6 : 2.5e-07 2.5e-07 (RCEX-011)
Information: Library Derived Res for layer METAL6 : 5.8e-05 3.2e-05 (RCEX-011)
Information: Library Derived Horizontal Cap : 2.1e-07 2.1e-07 (RCEX-011)
Information: Library Derived Horizontal Res : 0.00041 0.00022 (RCEX-011)
Information: Library Derived Vertical Cap : 2.3e-07 2.3e-07 (RCEX-011)
Information: Library Derived Vertical Res : 0.00028 0.00015 (RCEX-011)
Information: Using derived R and C coefficients. (RCEX-008)
Information: Using region-based R and C coefficients. (RCEX-013)
Information: Library Derived Via Res : 0.00061 0.00019 (RCEX-011)
LR: Layer METAL3: Average tracks per gcell 9.6, utilization 0.00
LR: Layer METAL4: Average tracks per gcell 8.2, utilization 0.00
LR: Layer METAL5: Average tracks per gcell 4.7, utilization 0.00
LR: Layer METAL6: Average tracks per gcell 4.3, utilization 0.00
LR: Clock routing service standing by
Using cts integrated global router
CTS: Blockage Aware Algorithm
Top-Level OCV Path Sharing not effective when timing derating is too low
[begin initializing data for legality checker]

Initializing Data Structure ...
INFO: legalizer_via_spacing_check_mode 0
  Reading technology information ...
    Technology table contains 6 routable metal layers
    This is considered as a 6-metal-layer design
    Reading library information from DB ...
  Reading misc information ...
    array <unit> has 0 vertical and 8 horizontal rows
    8 pre-routes for placement blockage/checking
    15 pre-routes for map congestion calculation
  Checking information read in ...
    design style = Horizontal masters, Horizontal rows

  Preprocessing design ...
    splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
CTS: all inverters have too large rise/fall delay skew
CTS: inverter inv0da: rise/fall delay skew = 0.204816 (> 0.200000) 
CTS: all inverters have too large rise/fall delay skew
CTS: inverter inv0da: rise/fall delay skew = 0.204816 (> 0.200000) 
CTS: Region Aware Algorithm is automatically turned off when design has no region or only has one region.
CTS-Warning: clock root not found
CTS: ==================================================
CTS: Start DRC fixing beyond exceptions
CTS: Blockage Aware Algorithm
CTS: Top-Level OCV Path Sharing not effective when timing derating is too low
[begin initializing data for legality checker]

Initializing Data Structure ...
INFO: legalizer_via_spacing_check_mode 0
  Reading technology information ...
    Technology table contains 6 routable metal layers
    This is considered as a 6-metal-layer design
    Reading library information from DB ...
  Reading misc information ...
    array <unit> has 0 vertical and 8 horizontal rows
    8 pre-routes for placement blockage/checking
    15 pre-routes for map congestion calculation
  Checking information read in ...
    design style = Horizontal masters, Horizontal rows

  Preprocessing design ...
    splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
CTS: all inverters have too large rise/fall delay skew
CTS: inverter inv0da: rise/fall delay skew = 0.204816 (> 0.200000) 
CTS: Region Aware Algorithm is automatically turned off when design has no region or only has one region.
CTS-Warning: clock root not found
CTS: DRC fixing initialization error. Abort
CTS: ==================================================
****************************************************************
Information: TLUPlus based RC computation is enabled. (RCEX-141)
****************************************************************
Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007)
Information: The RC model used is TLU+. (RCEX-015)
Information: Library Derived Cap for layer METAL : 1.9e-07 1.9e-07 (RCEX-011)
Information: Library Derived Res for layer METAL : 0.00065 0.00035 (RCEX-011)
Information: Library Derived Cap for layer METAL2 : 2.4e-07 2.4e-07 (RCEX-011)
Information: Library Derived Res for layer METAL2 : 0.00039 0.0002 (RCEX-011)
Information: Library Derived Cap for layer METAL3 : 2.4e-07 2.4e-07 (RCEX-011)
Information: Library Derived Res for layer METAL3 : 0.00039 0.0002 (RCEX-011)
Information: Library Derived Cap for layer METAL4 : 2e-07 1.9e-07 (RCEX-011)
Information: Library Derived Res for layer METAL4 : 0.00039 0.0002 (RCEX-011)
Information: Library Derived Cap for layer METAL5 : 2e-07 2e-07 (RCEX-011)
Information: Library Derived Res for layer METAL5 : 0.00019 0.0001 (RCEX-011)
Information: Library Derived Cap for layer METAL6 : 2.5e-07 2.5e-07 (RCEX-011)
Information: Library Derived Res for layer METAL6 : 5.8e-05 3.2e-05 (RCEX-011)
Information: Library Derived Horizontal Cap : 2.1e-07 2.1e-07 (RCEX-011)
Information: Library Derived Horizontal Res : 0.00041 0.00022 (RCEX-011)
Information: Library Derived Vertical Cap : 2.3e-07 2.3e-07 (RCEX-011)
Information: Library Derived Vertical Res : 0.00028 0.00015 (RCEX-011)
Information: Using derived R and C coefficients. (RCEX-008)
Information: Using region-based R and C coefficients. (RCEX-013)
Information: Library Derived Via Res : 0.00061 0.00019 (RCEX-011)
 CTS Successful 
Optimizing clock tree...
Operating Condition is max
No valid clocks specified, all clocks will be optimized
CTS: CTS Operating Condition(s): MAX(Worst) 
enable delay detour in ctdn

  Legalizing Placement
  --------------------

[begin initializing data for legality checker]

Initializing Data Structure ...
INFO: legalizer_via_spacing_check_mode 0
  Reading technology information ...
    Technology table contains 6 routable metal layers
    This is considered as a 6-metal-layer design
    Reading library information from DB ...
  Reading misc information ...
    array <unit> has 0 vertical and 8 horizontal rows
    8 pre-routes for placement blockage/checking
    15 pre-routes for map congestion calculation
  Checking information read in ...
    design style = Horizontal masters, Horizontal rows

  Preprocessing design ...
    splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
 
****************************************
  Report : Chip Summary
  Design : Sync_Rst_CompTop
  Version: K-2015.06-SP5-1
  Date   : Tue Feb 20 12:29:34 2018
****************************************
Std cell utilization: 79.69%  (510/(640-0))
(Non-fixed + Fixed)
Std cell utilization: 79.69%  (510/(640-0))
(Non-fixed only)
Chip area:            640      sites, bbox (5.00 5.00 37.80 34.52) um
Std cell area:        510      sites, (non-fixed:510    fixed:0)
                      64       cells, (non-fixed:64     fixed:0)
Macro cell area:      0        sites
                      0        cells
Placement blockages:  0        sites, (excluding fixed std cells)
                      0        sites, (include fixed std cells & chimney area)
                      0        sites, (complete p/g net blockages)
Routing blockages:    0        sites, (partial p/g net blockages)
                      0        sites, (routing blockages and signal pre-route)
Lib cell count:       13 
Avg. std cell width:  3.53 um 
Site array:           unit     (width: 0.41 um, height: 3.69 um, rows: 8)
Physical DB scale:    1000 db_unit = 1 um 

 
****************************************
  Report : pnet options
  Design : Sync_Rst_CompTop
  Version: K-2015.06-SP5-1
  Date   : Tue Feb 20 12:29:34 2018
****************************************


--------------------------------------------------------------------
Layer      Blockage   Min_width   Min_height   Via_additive     Density
--------------------------------------------------------------------
METAL      none          ---         ---       via additive      ---
METAL2     none          ---         ---       via additive      ---
METAL3     none          ---         ---       via additive      ---
METAL4     none          ---         ---       via additive      ---
METAL5     none          ---         ---       via additive      ---
METAL6     none          ---         ---       via additive      ---
 
****************************************
  Report : Legalize Displacement
  Design : Sync_Rst_CompTop
  Version: K-2015.06-SP5-1
  Date   : Tue Feb 20 12:29:34 2018
****************************************

No cell displacement.


  Placement Legalization Complete
  -------------------------------

Information: Updating database...
Unsetting the GR Options
LR: 0 out of 0 clock nets rerouted
LR: Clock routing service terminated
Invalidate design extracted status
Optimize clock tree UnSuccessful... Aborting clock_opt
0
 
Last edited by a moderator:

CTS-Warning: clock root not found - seems, you have incorrect "create_clock" command. Check the name of clock port?
 
"No valid clocks specified, all clocks will be optimized"
 

"create_clock" command from design vision. If thats the one, ive check my log its correct.
 

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