Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[No title]

Status
Not open for further replies.

shanmei

Advanced Member level 1
Joined
Jul 26, 2006
Messages
430
Helped
8
Reputation
16
Reaction score
8
Trophy points
1,298
Location
USA
Activity points
4,496
esd current flow path

In the figure, if there is a positive pulse at the input, the current flow is as the red line shows: from d1 to vdd, and go to M1. I don't understand that since M1 is off, why the current can go throught it? Thanks.

esd.png
 

Re: esd current flow path

Hi,

What is "M1". Do you have a partname? Datasheet?

Klaus
 
Re: esd current flow path

The FET has nothing to do with the input in red. There is a 0 ohm Vcc that absorbs the ESD. But there are 2 two pairs of diodes with a current limiting R in between. THe FET is only controlled by Cap voltage.
 
Re: esd current flow path

ESD voltage is not DC, that's your problem. The C-R network
is supposed to trigger M1 to conduct (although there may be
more current taken in snapback of the parasitic BJT, than the
channel, depending on device type and design.). High dV/dt
on the rail-difference is your triggering feature. I'd infer that
the FET is PMOS given the trigger network, but PMOS have no
useful snapback and in my experience have blown up (gate
rupture. voltage mode) too easily as a result.

Furthermore such simple schemes are prone to release too
early against a HBM strike's internal time constant, letting
(say) the last kV or two from a 4kV strike be applied to the
FET at a dV/dt that fails to trigger, so roasts the clamp
and/or what it was supposed to protect as a result. A good
central clamp will also have a DC "backstop" and probably a
gain lineup in front of the main FET to make triggering more
dependable, across the threat-envelope.
 
Re: esd current flow path

Yes, usually nMOSFETs are used in RC-triggered ESD clamps, and nMOSFET gate is connected to the node between R and C through a buffer (an inverter or an odd number of inverters).
 
Re: esd current flow path

I forgot the inverter, thanks.

esd1.png

- - - Updated - - -

Hi,

What is "M1". Do you have a partname? Datasheet?

Klaus

M1 is just a large transistor. It is not board level design. It's transistor level design for the IC.

- - - Updated - - -

dick_freebird;. I'd infer that the FET is PMOS given the trigger network.[/QUOTE said:
Thanks. I forget that there is a inverter before M1.

- - - Updated - - -

If there is a large positive voltage spike on the input pad , the diode d1 conducts, then current goes into vdd. Whether power supply vdd is also has a positve voltage spike caused by the input positive spike?

If vdd has no positive spike from the input pad, then the gate of M1 is 0, M1 is off, the discharge current can't go through M1.

So the input positive spike can lead to the vdd positive spike, right? Thanks.
 

Re: esd current flow path

Yes, you have just explained how RC-triggered ESD clamp works :)
 

Re: esd current flow path

Is the power clamp works at the moment of the startup?

When the Vdd rises from 0 to 1, input signal of inverter has a slow ramp due to the large RC, making the time interval that output voltage of the inverter to be 1, wihch turns on transistor M1 to discharge current. After the time inverval, M1 is off.
 

Re: esd current flow path

I believe that the time constant of RC clamp should be much shorter than the ramp up time of the startup, but much longer than ESD even time constant.
So that during startup ESD clamp stays closed and does not conduct any current.
 

Re: esd current flow path

M1 is a gate coupled NMOS (gcnmos) for ESD. I don't recall seeing the RC in that configuration. Usually the C is between the drain and gate with the R between the gate and GND.
 

Re: esd current flow path

Additionally, M1 is a clamp between VDD and GND that gets activated if the IR drop along VDD gets too high. It will shunt current to GND. I have placed these clamps at I/O pads and PWR/GND pads. I doubt you would see any current back through the input (blue trace).
 

Re: esd current flow path

ESD can be either polarity (in theory - maybe once installed
in a higher level assembly, some of the pin-pin loops are no
longer accessible). This is why there should be a back diode.
MOS diodes are inferior for conductance-density, as a rule.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top