harpv
Member level 4
Hi,
If there's a generated clock which is a divided down version of an oscillator clock, how would the edge-to-edge and duty cycle uncertainties be propagated from source clock to the generated clock?
Say there's an oscillator clock clk_osc
And a generated clock clk_gen_osc from the clk_osc
I'm putting an edge-to-edge uncertainty of 1% and 10% on duty for the oscillator clock as follows :
My question is how will the uncertainties of clk_gen_osc look like.
Thanks in advance.
If there's a generated clock which is a divided down version of an oscillator clock, how would the edge-to-edge and duty cycle uncertainties be propagated from source clock to the generated clock?
Say there's an oscillator clock clk_osc
Code:
create_clock -name clk_osc \
-period 100 \
u_osc/out
And a generated clock clk_gen_osc from the clk_osc
Code:
create_generated_clock -name clk_gen_osc \
-divide_by 2 \
-source [get_pins u_osc/out] \
u_clk_gen/out
I'm putting an edge-to-edge uncertainty of 1% and 10% on duty for the oscillator clock as follows :
Code:
# edge-to-edge
set_clock_uncertainty -setup [expr 100*1/100] -rise_from clk_osc -rise_to clk_osc
set_clock_uncertainty -setup [expr 100*1/100] -fall_from clk_osc -fall_to clk_osc
# duty cycle
set_clock_uncertainty -setup [expr 100*10/100] -rise_from clk_osc -fall_to clk_osc
set_clock_uncertainty -setup [expr 100*10/100] -fall_from clk_osc -rise_to clk_osc
My question is how will the uncertainties of clk_gen_osc look like.
- Will it be same as clk_osc?
- Will the edge-to-edge uncertainty of clk_osc become duty-uncertainty of clk_gen_osc, and edge-to-edge uncertainty of clk_gen_osc twice the edge-to-edge uncertainty of clk_osc ?
- Will the uncertainty depend on whether the generated clock is from a flop based divider or pulse dropped version through a clock gate ?
Thanks in advance.