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  1. #1
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    unmatched nets in the layout

    Hi guys, i badly need your help. i have been bothered by this error that says: "unmatched net in the layout"
    i wondered whats wrong with my layout. i have done checking and tracing my schematic and layout many times, i also did relayouts many times. my layout looks like this whenever i click the error Click image for larger version. 

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ID:	144581 Click image for larger version. 

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ID:	144580 This is in 65nm Tech Custom Compiler. and this is what my schematic looks like Click image for larger version. 

Name:	Capture3.JPG 
Views:	13 
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ID:	144582

  2. #2
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    Re: unmatched nets in the layout

    To begin with, I see some "gnd" globals that are never
    appropriate for on-chip use. These should be going to
    a schematic supply pin or on-chip-appropriate ground
    global (gnda!, gndd!, vssa!, vssd!, ...) that does not
    attach to the zero node.

    gnd! should be your measurement reference plane.
    Any other use is "iffy" at best and usually ignores a
    bunch of realities (such as packaging and PCB parasitic
    features).

    It's hard to deduce from the report or layout view
    what the error is, but it seems to think there's a
    short. Probing schematic mismatched and layout
    mismatched nets one by one ought to home in on
    what's messed up. Sometimes you have to go at it
    visually and hope your eyes recognize "what should
    have been".


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    Re: unmatched nets in the layout

    A better layout should have a "Private Ground" such as my_gnd or similar.
    As mentioned above, gnd! and likewise grounds are Global Grounds and they should be used in digital gate based layouts.


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    •   Alt14th February 2018, 23:15

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    Re: unmatched nets in the layout

    Your LVS tool report tells you about the most likely cause of the error: "Potential shorted nets in the layout".
    Apparently, four schematic nets got shorted on the layout - so the LVS tool cannot establish a one-to-one correspondence (matching) between four schematic nets and one layout net.

    Net name "N_2" sounds like an internal net name, I would expect its name be inherited from one of the schematic net names.
    But I do not see a single internal net in your schematic - there are only external nets, with ports on them.

    Did LVS tool report the schematic net names that got shorted?

    I have a software tool that helps debug and identify the root causes of net shorts - write me a private message if you need a help.

    By the way, did you try using your LBVS system debugging capabilities, to resolve net shorts issue? (are you using Calibre?).

    Max


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    Re: unmatched nets in the layout

    Thanks for the response.
    Now i am very curious of what happened when the sources of my two nmos transistors Attachment 144640 are fused into 1 input, the LVS Error is Clean Attachment 144641 Attachment 144642

    However, whenever i use my original circuit wherein two nmos transistors have their own inputs connected to the source Attachment 144643 Attachment 144644, the LVS Error says these following error information in the images below:

    Attachment 144645, it also says this Attachment 144646 i dont understand why it says that the net57 and net54 in the layout is N/A, i have named my pin the layout the net57 and net54, and in the same order with the schematic. and also this Click image for larger version. 

Name:	nmos1.JPG 
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ID:	144647 even though i have the same transistor with the same aspect ratio in the layout and schematic.



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    Re: unmatched nets in the layout

    Your attachments are invalid, it's impossible to make a sense out of your message without seeing the pictures...



    •   Alt16th February 2018, 06:30

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    Re: unmatched nets in the layout

    Quote Originally Posted by timof View Post
    Your attachments are invalid, it's impossible to make a sense out of your message without seeing the pictures...
    i already triple checked it. and it is still the same



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    Re: unmatched nets in the layout

    What is the same - LVS errors, or attachment being invalid?
    Can you open links yourself, to your attachments?



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    Re: unmatched nets in the layout

    Quote Originally Posted by timof View Post
    What is the same - LVS errors, or attachment being invalid?
    Can you open links yourself, to your attachments?
    i got this error Click image for larger version. 

Name:	Capture.JPG 
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ID:	144687 Click image for larger version. 

Name:	Capture.JPG 
Views:	3 
Size:	21.0 KB 
ID:	144688 Click image for larger version. 

Name:	Capture.JPG 
Views:	3 
Size:	16.9 KB 
ID:	144689

    i already triple checked my Layout, and it matches the schematic but still i got this problem. I am using Custom Compiler 65nm CMOS Tech.



    •   Alt17th February 2018, 17:35

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  10. #10
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    Re: unmatched nets in the layout

    Your nets C and D appear to be merged (and hence missing in the layout) with some other nets - trace their connectivity and see what's wrong.
    LVS system should tell what nets are they merged into.

    You did not explain what changes did you do to your schematic or layout that LVS errors are now different.



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    Re: unmatched nets in the layout

    Quote Originally Posted by timof View Post
    Your nets C and D appear to be merged (and hence missing in the layout) with some other nets - trace their connectivity and see what's wrong.
    LVS system should tell what nets are they merged into.

    You did not explain what changes did you do to your schematic or layout that LVS errors are now different.
    i am sorry for not stating what i did to my layout to remove previous errors, what i did is that i added some layers in my transistors.

    The LVS System doesnt say what nets are merged

    - - - Updated - - -

    i think this is the main source of the error, Click image for larger version. 

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ID:	144694
    and i dont know how to fix it.



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    Re: unmatched nets in the layout

    Are you sure that the LVS does not produce some kind of
    report file that lists every error? I know I always got one
    (Cadence IC6, Silvaco Guardian). Maybe you have to tell
    it to cough it up, or maybe it just goes somewhere you
    don't usually look (like in the barf stream of the main log
    file).

    Can you not "display all merged nets" and see some kind
    of listing?



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    Re: unmatched nets in the layout

    Quote Originally Posted by dick_freebird View Post
    Are you sure that the LVS does not produce some kind of
    report file that lists every error? I know I always got one
    (Cadence IC6, Silvaco Guardian). Maybe you have to tell
    it to cough it up, or maybe it just goes somewhere you
    don't usually look (like in the barf stream of the main log
    file).

    Can you not "display all merged nets" and see some kind
    of listing?
    The error says that in my Schematic, i am using nch_lvt which is true, but in the layout it says that i am using nch_lvt_mac, now i am very much confused what "MAC" means. I just copied the same layers used in nch_lvt in our TSMC65nm Library but the error stays the same.



  14. #14
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    Re: unmatched nets in the layout

    Quote Originally Posted by bwarlord01 View Post
    ... in the layout ... i am using nch_lvt_mac, now i am very much confused what "MAC" means.
    See this post:
    nch_lvt_mac device ... models mismatch characteristics of low-Vt NMOS.
    Use the nch_lvt_mac symbol in your schematic, too!



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