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    Virtuoso 6.1. 6 Unable to see DC operating pts in Post layout Simulation (Calibre)

    I have created a test bench with calibre view .
    DC simulation is running fine. I can sweep DC variables and see the variation of output with them.
    But, I am unable to see the DC operating points.

    I had opted for "Save DC operating Points" in Analog Design Envronment (ADE).
    However, "Print DC Operating points" is not working for extracted view (calibre).
    It works for schematic view.


    The ac results of post layout simulation do not meet the specs.
    Hence, I need to know whether all transistors are operating in saturation.
    This can only be done through DC operating point (region) option.

    Kindly provide the solution
    Last edited by deveshkm; 14th February 2018 at 07:22. Reason: more meaningful title

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    Re: Cadence Virtuoso 6.1. 6 Unable to see DC operating points in extracted view (Cali

    What is the purpose of viewing DC Operating Point on an Extracted View ?? Roughly Nothing will be different.



    •   Alt14th February 2018, 07:03

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    Re: Cadence Virtuoso 6.1. 6 Unable to see DC operating points in extracted view (Cali

    Quote Originally Posted by BigBoss View Post
    What is the purpose of viewing DC Operating Point on an Extracted View ?? Roughly Nothing will be different.
    Thanks for responding.

    The post layout results of ac analysis are incorrect.
    I suspect there is significant mismatch.

    The DC operating points of transistors in the post layout simulation can indicate the transistors which are not working in correct regions.
    I had done the layout of several small blocks before merging them for the complete layout.
    It can help focus on those transistors, where there is more mismatch



    •   Alt14th February 2018, 07:20

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    Re: Cadence Virtuoso 6.1. 6 Unable to see DC operating points in extracted view (Cali

    Quote Originally Posted by deveshkm View Post
    Thanks for responding.

    The post layout results of ac analysis are incorrect.
    I suspect there is significant mismatch.

    The DC operating points of transistors in the post layout simulation can indicate the transistors which are not working in correct regions.
    I had done the layout of several small blocks before merging them for the complete layout.
    It can help focus on those transistors, where there is more mismatch
    If LVS has passed well, there should principally not be any difference between schematic and layout circuit.So, if the frequency is not extremely high why AC simulation results will be different ??
    There is either a LVS mismatch/discrepancy or something else.PDKs may sometimes have some extraction failures, cross-check with your IT responsible.



    •   Alt14th February 2018, 15:19

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    Re: Virtuoso 6.1. 6 Unable to see DC operating pts in Post layout Simulation (Calibre

    Quote Originally Posted by deveshkm View Post
    I had opted for "Save DC operating Points" in Analog Design Envronment (ADE).
    However, "Print DC Operating points" is not working for extracted view (calibre).
    It works for schematic view.
    Backannotation only works back into the schematic view, never into the extracted view.

    After simulation of the extracted view netlist, the new - possibly changed - DC operation points are backannotated into the schematic view. At least this had been the case after DIVA or ASSURA extraction. May be this doesn't work with CALIBRE ?



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    Re: Cadence Virtuoso 6.1. 6 Unable to see DC operating points in extracted view (Cali

    OP does not care about capacitance. If your extraction
    is not RC (C-only) then OP also does not know about
    layout effects there.

    There's probably some Spectre option to dump all OP
    info for every device and then you could sift that
    somehow (grep, Excel) from the dump file.

    You could of course just probe around looking at
    drain-gate voltages for anything that's negative.
    Is that so terribly tedious?

    If you think there is layout induced mismatch (of
    the sort that even a RC extract could "see") then
    you ought to be able to probe and see. There
    probably aren't that many matching-critical parts
    and you should know them.



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    Re: Cadence Virtuoso 6.1. 6 Unable to see DC operating points in extracted view (Cali

    Quote Originally Posted by BigBoss View Post
    If LVS has passed well, there should principally not be any difference between schematic and layout circuit.
    That was probably true in very old (let's say, 1 um and above) technologies.
    But this is definitely not true for more or less advanced technologies.
    As an example - in latest technologies (16/10/7nm), oscillation frequency can decrease by a factor of 2x to 3x due to parasitics (parasitic C but mainly parasitic R).

    An indirect proof of my point is a presence of "parasitic extraction" step in IC design flow - why would you need it if there is no difference?

    - - - Updated - - -

    deveshkm - post-layout simulations being significantly different form schematic simulation results is a common problem (especially in latest, FinFET technologies - 16nm, 14nm, 10nm, 7nm, 5nm, ...).
    Usually this is caused by layout parasitics.

    As a quick suggestion for debugging - do the extraction in different modes - 1. device only (no R or C - but with device instances having layout-dependent parameters), 2. C only, 3. R only, 4. full distributed RC.
    Then run simulations for each, and see where the results start failing (significantly different from schematic simulations).

    If you suspect this is caused by net / device mismatch - there are software tools that can detect and debug such mismatched (accounting for parasitics and layout-dependent effects) much more efficiently than trying to run post-layout simulations and then trying to make sense out of that.
    I can help you with that.

    Max



    •   Alt15th February 2018, 00:13

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    Re: Cadence Virtuoso 6.1. 6 Unable to see DC operating points in extracted view (Cali

    Quote Originally Posted by timof View Post
    That was probably true in very old (let's say, 1 um and above) technologies.
    But this is definitely not true for more or less advanced technologies.
    As an example - in latest technologies (16/10/7nm), oscillation frequency can decrease by a factor of 2x to 3x due to parasitics (parasitic C but mainly parasitic R).
    An indirect proof of my point is a presence of "parasitic extraction" step in IC design flow - why would you need it if there is no difference?
    Max
    LVS does not take the parasitic elements into account.It checks layout versus schematic in term of component based comparison.
    Parasitic Extraction is another history.



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    Re: Cadence Virtuoso 6.1. 6 Unable to see DC operating points in extracted view (Cali

    Quote Originally Posted by BigBoss View Post
    LVS does not take the parasitic elements into account.It checks layout versus schematic in term of component based comparison.
    Parasitic Extraction is another history.
    Yes, but original poster said - "The ac results of post layout simulation do not meet the specs".
    "post layout" means after parasitic extraction, where all parasitics of the layout, as well as other layout-dependent effects are taken into account.



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