+ Post New Thread
Results 1 to 2 of 2
  1. #1
    Full Member level 4
    Points: 1,210, Level: 7

    Join Date
    Feb 2016
    Posts
    206
    Helped
    0 / 0
    Points
    1,210
    Level
    7

    Questions on Fanout of 4

    After some math, it can be shown that the minimum delay is achieved when the load is driven by a chain of N inverters, each successive inverter ~4x larger than the previous; N ~ log4(Cload/Cin)
    In the absence of parasitic capacitances (drain diffusion capacitance and wire capacitance), the result is "a fan out of e" (now N ~ ln(Cload/Cin))
    For https://en.wikipedia.org/wiki/FO4 , could anyone help to derive the above two equations under different conditions ?

    •   Alt13th February 2018, 15:29

      advertising

        
       

  2. #2
    Advanced Member level 4
    Points: 5,363, Level: 17

    Join Date
    Apr 2016
    Posts
    1,126
    Helped
    202 / 202
    Points
    5,363
    Level
    17

    Re: Questions on Fanout of 4

    Quote Originally Posted by promach View Post
    For https://en.wikipedia.org/wiki/FO4 , could anyone help to derive the above two equations under different conditions ?
    define 'different conditions'. if the load is changing the equations are exactly the same. you would need a process that is really different from CMOS to effectively need different equations/assumptions.
    Really, I am not Sam.



--[[ ]]--