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CMOS Inverter Worst case and best case delay analysis

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ANALA

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Greetings,

I have simulated a CMOS inverter in LTspice using the following specifications
Supply voltage 0.2V
NMOS & PMOS Length(L)=32n
NMOS Width(W) =32n
PMOS Width(W) =64n
NMOS Drain/Source Area=2f
PMOS Drain/Source Area=4f
NMOS Drain/Source Perimeter=192n
PMOS Drain/Source Perimeter=256n
Threshold Voltage(Vth0) NMOS=0.3558
Threshold Voltage(Vth0) PMOS=-0.24123

...How do i perform the best case and worst case delay analysis?
 

You need the best case and worst case process variance data including their voltage & temperature behavior. With this data set, run simulation analyses at your expected best case and worst case voltage & temperature values. Even better: run Monte Carlo analysis with these parameters.
 

So once i get the SS and FF model files, is that using thses model file i just need to run my simulations?

- - - Updated - - -

I have downloaded 32nm models for TT, FF,and SS from ptm website(http://ptm.asu.edu/). I want to test these on a cmos inverter using LTspice. Kindly tell me how should i proceed.
 
Last edited:

ANALA said:
So once i get the SS and FF model files, is that using thses model file i just need to run my simulations?

Kindly tell me how should i proceed.
Click to expand...

Right. Run the SS analysis at the lowest expected supply voltage and the highest expected temperature. The FF analysis at the highest expected supply voltage and the lowest expected temperature.
 

Not sure LTSpice is at all appropriate for such work,
those geometries tend to want fancy fussy modern
models.Maybe if this is just an exercise, nobody cares.
I doubt anyone would be using LTSpice to do an actual
chip design, since it's uncoupled to any layout tools.

I do not see fanout mentioned; min delay would be FO=1
(FO=0 being trivial and useless) and there would be a
design style / library imposed upper limit to fanout and
wireload (which you would also specify or have specified
to you - wild guess as to max run of interconnect).
 

and what if the SS and FF model files are not available?
 

ANALA said:
and what if the SS and FF model files are not available?
Click to expand...

You can still estimate the delay variance from such variances of a similar process.
 

Some things like the co-variances of TOXP & TOXN,
deltalP and deltalN, u0P and u0N, VTP and VTN are
going to elude you if looking at WAT limits alone, and
using worst case for each may be unrealistically bad
(some are anticorrelated in part).

That said, you could -assert- some conditions and
let "whoever" criticize the details of that choice.
Like VT +/- 20%, Tox +/- 10%, Leff +/- 10%
(whatever deltaL makes that so) and so on.
Contemplate, add "kxxxx*" factors to the relevant
SPICE model cards, make something up for the "k"
values and loop it nested, then sort for the worst
you encountered.
 

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