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accessing memory address in verilog

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jasi

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Hello everyone,
how to access memory address of a variable in verilog.
 

Can you please post a portion of your code related to the above query..

And which memory address are you talking about ?
 

Can you please post a portion of your code related to the above query..

And which memory address are you talking about ?


i just declare a variable, then value is given to that variable . For example reg a<= 100; .i need to find the address of that variable "a" which contain 100 using verilog.
 

The address is undefined. Indeed it is up to you to write a description of a system where an address would be accessible and make sense.
 

Hi,

I assume you are thinking "software" style, but verilog is a "hardware" description language.
You have to treat them differently.

While with a microcontroller you always have a "memory" with true address bus and databus.
But with hardware it may be just a register.

Imagine you have discrete hardware (no microcontroller).
You won´t design an 8 bit counter as SRAM.
But most probably you will store sampled audio data in an SRAM.

Klaus
 

how to access memory address of a variable in verilog.

You don't - "Addresses" aren't part of the HDL scope.
You have to describe logic that's "address aware" for it to be addressable...
 

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