Protecting a DPAK NFET from ESD damage

Hello,
We have DPAK NFETs right close to the edge of the PCB, and we suspect ESD damage to them.
Will adding a diode from Gate to source (cathode to gate), in any way reduce the ESD risk to these FETs?

They should also have a series R to current limit the clamp.

If not terminated that's a problem in handling.

I remember newbie EEs blowing the TEK active Diff probes with FET inputs rated for only 25V. Thats why they had ground shunts when not in use. The service tech was always shaking her head doing repairs.

They should also have a series R to current limit the clamp.

If not terminated that's a problem in handling.

Click to expand...

Thanks, you mean they should have a resistor gate to source too?

Thanks, ..the clamp' you are referring to is the clamp circuit i referred to in my other post a while back?

Hi,

Will adding a diode from Gate to source (cathode to gate), in any way reduce the ESD risk to these FETs?

Click to expand...

It may reduce the risk caused by negative ESD voltages at Gate-source.
It won't reduce the risk caused by positive voltages across GS.
It won't reduce the risk caused by ESD on DS.

Klaus

WHY do you suspect ESD damage? Why do you assume it's a negative spike on the gate? If you just arbitrarily add parts to a circuit without understanding the underlying problem you are doomed to a life of mediocre designs.

A zener is often shown as a G-S clamp (perhaps more for
in-use EOS, than in-handling ESD). There ought to be a
series resistor, pin-G as said earlier. The question of where
the "ESD" damage is incurred, and what form, is important.
If you have multiple of these than a rack of catch-diodes
and a single central clamp can be more economical and
perhaps better-performing (zeners can have limited
robustness, themselves, against ampere-range ESD peak
currents).

If these are field returns en masse I'd be looking more
at EOS than ESD. Characterize the pin(s) failure threshold
(pulsed / TLP, and DC) and you'll know what it takes to
break it; send some victims out with an ESD surveyor
and follow them through their trail to see where any
such threats lie in wait, knowing what you are looking
for.

You ought to test your designs for EOS ( which is the preferred description that includes ESD) and use TVS as required.

I recall our std practice used a Shaeffer HBM probe and injected 100 discharges 15kV no damage and no functional failure was our Corp spec. Above 10kV human intervention (reset) was allowed.

https://www.google.ca/search?num=20...31k1j0i10k1j0i13k1j0i22i10i30k1.0.s1qR-9VzjsE

There are millions of purpose built ESD suppression devices (TVS Diodes among other names) for any voltage and in any size.

As mentioned you want a zener type clamp of perhaps 15V (above your gate drive, below the Vgs limit).