stelliestech
Newbie level 1
Hi
The time has arrived that we need to use DDR2. Up to now we managed to avoid this, by using PSRAM. So, it took a week to read/scan most of the info available by product vendors (Xilinx and Micron) and also to read a load of articles about SI. We started with the PCB design. We have worked with BGA in the past and we like to use capped vias right under the BGA pads. This is more expensive, but works for us and simplifies the design.
The first decision: number of layers? We are only using a single DDR2 chip and it sits right next to the FPGA ... no trace is longer than 27 mm. So, we decided on a 4-layer board with signals on the top and bottom layers. The basic routing was done = placement of vias and traces. Data and address lines are on the bottom layer (2 vias for each trace) and control and clock signals are on the top layer (no vias).
Next step: trace length tuning. This is where it got difficult. We can match the length of all the traces but the propagation delay for traces with vias is difficult to estimate.
The question is: is it possible to get SI by only using estimates for the via propagation delays and matching trace lengths? Or, would you recommend using a simulator like HyperLynx? I am not sure about the price for HyperLynx and I guess it also has a learning curve.
The other question, of course, is what are the trace impedances and are termination resistors required. It feels a bit strange to add termination resistors when the 0402 resistor barely fits between the FPGA and DDR2.
What is your experience with DDR2 and SI? I am just not sure if it is necessary diving into a full analysis for this design. On the other hand, I certainly don't want to sit with SI problems.
Looking forward to your replies.
The time has arrived that we need to use DDR2. Up to now we managed to avoid this, by using PSRAM. So, it took a week to read/scan most of the info available by product vendors (Xilinx and Micron) and also to read a load of articles about SI. We started with the PCB design. We have worked with BGA in the past and we like to use capped vias right under the BGA pads. This is more expensive, but works for us and simplifies the design.
The first decision: number of layers? We are only using a single DDR2 chip and it sits right next to the FPGA ... no trace is longer than 27 mm. So, we decided on a 4-layer board with signals on the top and bottom layers. The basic routing was done = placement of vias and traces. Data and address lines are on the bottom layer (2 vias for each trace) and control and clock signals are on the top layer (no vias).
Next step: trace length tuning. This is where it got difficult. We can match the length of all the traces but the propagation delay for traces with vias is difficult to estimate.
The question is: is it possible to get SI by only using estimates for the via propagation delays and matching trace lengths? Or, would you recommend using a simulator like HyperLynx? I am not sure about the price for HyperLynx and I guess it also has a learning curve.
The other question, of course, is what are the trace impedances and are termination resistors required. It feels a bit strange to add termination resistors when the 0402 resistor barely fits between the FPGA and DDR2.
What is your experience with DDR2 and SI? I am just not sure if it is necessary diving into a full analysis for this design. On the other hand, I certainly don't want to sit with SI problems.
Looking forward to your replies.