fadia
Newbie level 2
I want to test my register file before connecting it to ALU. So I wrote a testbench for my register file.
and this is my testbench
So with above conditions the testbench output rd1 and rd2 will be don't care, but when I set all the input to same number the output will work and will be same as input. I know this sound to me the output is following the input, but the schematic doesn't show that. So what could be reason for this situation.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 // 16 x 32 register file with two read, 1 write port module regfile( input logic clk, we3, input logic [31:0] a1, a2, a3, input logic [31:0] wd3, output logic [31:0] rd1, rd2); logic [31:0] RAM[15:0]; //16 regsiters assign rd1 = RAM[a1]; // asynchronous read assign rd2 = RAM[a2]; always @(posedge clk) begin // synchronous write if (we3) RAM[a3] <= wd3; end endmodule
and this is my testbench
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module regfile_tb(); logic clk=0, we3; logic [31:0] a1, a2, a3; logic [31:0] wd3; logic [31:0] rd1, rd2; regfile uut(.clk(clk), .we3(we3), .a1(a1), .a2(a2), .a3(a3), .wd3(wd3), .rd1(rd1), .rd2(rd2)); always #5 clk = ~clk; initial begin #2 we3=1; a1=4; a2=5; wd3=15; a3=15; #10 $finish; end endmodule
So with above conditions the testbench output rd1 and rd2 will be don't care, but when I set all the input to same number the output will work and will be same as input. I know this sound to me the output is following the input, but the schematic doesn't show that. So what could be reason for this situation.
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