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I am assuming that you are using a Xilinx 7 series FPGA.
This is all clearly explained in the 7 Series Select I/O Resources User Guide (UG471).
Download it and read it. See the section on IDELAYCTRL (and IDELAY/ODELAY).
In short, the IDELAYCTRL takes in a reference clock which it uses to calibrate the delay of each tap of the IDELAY/ODELAY. Each tap is calibrated to 1/64 of the period of the reference clock supplied to the IDELAYCTRL. Depending on speed grade, the IDELAYCTRL reference clock is allowed to be 200MHz, 300MHz, or 400MHz, which results in tap sizes of 78ps, 56ps, or 39ps respectively. The LOCKED signal of the IDELAYCTRL indicates when the taps have been successfully calibrated, which will happen shortly after power-up (or IDELAYCTRL reset).
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