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[SOLVED] Synopsys IC Compiler warning and Error

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dayana42200

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Hi all,

I get this warning when I run IC Compiler in Synopsys. These are some of the errors that I get.

Warning: Unable to resolve reference 'LookUpTable_ComputeDataWidth8_0' in 'ProcessingElement'. (LINK-5)
Info: Creating auto CEL.
Error: Can not create instance master 'LookUpTable_ComputeDataWidth8_0' in FRAM view. (MWDC-001)
Error: Cannot find instance in CEL view 'LUT'. (MWDC-005)

LINK-5 (warning) Unable to resolve reference '%s' in '%s'.


DESCRIPTION
This warning is issued when a suitable design can not be found to link
a cell reference to. This will result in any cells using that reference
being left as "black boxes". Generally this will happen because of one
of two reasons: (1) either a design with the same name as the reference
does not exist in the database, link libraries and the directories
specified by the search_path, or, (2) the design exists but there are
port mismatches between the reference and the design. In the second
case an additional error message indicating the exact nature of the
mismatch would be given.

If this error occurs while building a synthetic library part, you prob-
ably need to use "set_local_link_library" within your implementation
description. Please refer to the section "Adding Hierarchy-Control
Directives" in the DesignWare Developer Guide.

MWDC-001 (error) Can not create instance master '%s' in FRAM view.


DESCRIPTION
You receive the error message because for some reasons, the instance
master can't be create in FRAM view. For instance, please check the
read and write permission for FRAM directory, please check if the
instance master name is longer than 1024 chars, the instance master
should not existed.

MWDC-005 (error) Cannot find instance in CEL view '%s'.


DESCRIPTION
User should have read permission for CEL view, and check that the
instance name being input is correct or not.

What does it mean? I dont really understand.
 
Last edited by a moderator:

The reason is clearly mentioned under "DESCRIPTION" <1> and <2> in English language.
In #2 you have another hint as to what you should be checking.
Please re-check your design. Check that all paths are existing.
 
I mean your hierarchy is broken. You are missing files or whole libraries.

I am sorry. I still dont understand.
I have all the verilog code kept in a folder.
The ddc file also is in that folder.
I have no error in design vision.
The waveform also works.

Do I have to save all my sub modules in ddc file n import all of it in IC Compiler?
 

"Error: Can not create instance master 'LookUpTable_ComputeDataWidth8_0' in FRAM view. (MWDC-001)"

The tool is giving you all the hints you could ever ask for. What is this instance? Why is it an error?
 

Design vision works with verilog code and ddc files. IC Compiler works with ddc and Milkyway libraries (CEL, FRAM). Did you added any mw-libs as reference to your working milkyway library?
 

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