razer6
Newbie level 3
Hi,
I am trying to perform a post-synthesis simulation.
For synthesis, I am using Cadence RTL Compiler 14.2and my target technology is UMC 65nm.
To perform the simulation, I write out the SDF file after finishing synthesis and then back-annotate my synthesis netlist with it.
Creating the SDF file is done using the following command:
The SDF file then gets compiled to out.sdf.gz.X using ncsdfc.
However, when running the simulation, I get timing violations for various flipflops.
When looking to this annotation stats, I see following values:
Annotation completed with 0 Errors and 176 Warnings
SDF statistics: No. of Pathdelays = 100497 Annotated = 88.82% -- No. of Tchecks = 8036 Annotated = 0.00%
The warnings are all related to VSS/VDD so I don't care for now:
ncelab: *W,SDFDSM: Attempt to annotate interconnect delay to non-existent load VSSIO at
But what's strange here is that the timing checks are not annotated. Therefore, the default (dummy) timing checks are used from the cell definition I got from the library, which fail.
To investigate this further, I opened the SDF file and looked for the cell definition of a failing flipflop:
When I compare this with the Verilog cell definition I get from the library, I see matching timing checks, which should be overlayed by the SDF timing checks.
However, as shown in the annotation statistics, no timing checks have been annotated.
Can someone help me how to properly annotate the Verilog netlist with my SDF file such that the timing checks are also applied?
I already looked into different directions but did not find anything special.
Best regards,
Robert
I am trying to perform a post-synthesis simulation.
For synthesis, I am using Cadence RTL Compiler 14.2and my target technology is UMC 65nm.
To perform the simulation, I write out the SDF file after finishing synthesis and then back-annotate my synthesis netlist with it.
Creating the SDF file is done using the following command:
Code:
write_sdf -precision 4 -nonegchecks -edges check_edge -setuphold merge_always out.sdf.gzThe SDF file then gets compiled to out.sdf.gz.X using ncsdfc.
However, when running the simulation, I get timing violations for various flipflops.
When looking to this annotation stats, I see following values:
Annotation completed with 0 Errors and 176 Warnings
SDF statistics: No. of Pathdelays = 100497 Annotated = 88.82% -- No. of Tchecks = 8036 Annotated = 0.00%
The warnings are all related to VSS/VDD so I don't care for now:
ncelab: *W,SDFDSM: Attempt to annotate interconnect delay to non-existent load VSSIO at
But what's strange here is that the timing checks are not annotated. Therefore, the default (dummy) timing checks are used from the cell definition I got from the library, which fail.
To investigate this further, I opened the SDF file and looked for the cell definition of a failing flipflop:
Code:
(CELL
(CELLTYPE "DFQRM2RA")
(INSTANCE duv.reg)
(DELAY
(ABSOLUTE
(PORT RB (::0.0))
(PORT CK (::0.0))
(PORT D (::0.0))
(IOPATH RB Q () (::64))
(IOPATH CK Q (::147) (::141))
)
)
(TIMINGCHECK
(RECREM (posedge RB) (posedge CK) (::0.0) (::124))
(SETUPHOLD (negedge D) (COND ENABLE_RB===1'b1 (posedge CK)) (::23) (::10))
(SETUPHOLD (posedge D) (COND ENABLE_RB===1'b1 (posedge CK)) (::37) (::0.0))
(WIDTH (negedge RB) (::50.72))
(WIDTH (posedge CK) (::56.22))
(WIDTH (negedge CK) (::58.8))
)
)When I compare this with the Verilog cell definition I get from the library, I see matching timing checks, which should be overlayed by the SDF timing checks.
Code:
specify
// arc CK --> Q
(posedge CK => (Q : D)) = (1.0,1.0);
// arc RB --> Qx
(RB => Q) = (1.0,1.0);
$width(negedge CK,1.0,0,notifier);
$width(posedge CK,1.0,0,notifier);
// setuphold D- CK-LH
$setuphold(posedge CK &&& (ENABLE_RB === 1'b1),
negedge D &&& (ENABLE_RB === 1'b1),
1.0,1.0,notifier,,,CK$delay,D$delay);
// setuphold D- CK-LH
$setuphold(posedge CK &&& (ENABLE_RB === 1'b1),
posedge D &&& (ENABLE_RB === 1'b1),
1.0,1.0,notifier,,,CK$delay,D$delay);
// recrem RB-CK-posedge
$recrem(posedge RB,posedge CK,1.0,1.0,notifier,,,RB$delay,CK$delay);
$width(negedge RB,1.0,0,notifier);
endspecifyHowever, as shown in the annotation statistics, no timing checks have been annotated.
Can someone help me how to properly annotate the Verilog netlist with my SDF file such that the timing checks are also applied?
I already looked into different directions but did not find anything special.
Best regards,
Robert
Last edited: