vinitkanojia
Newbie level 2
Hi,
I am trying to integrate a module UVC at chip level. Objective is to pick the uvc from the library. The behavioral model in the UVC requires a project specific hack. After inheriting a new class from the parent class, I make the required changes in the derived class and try to override the same from my base test. It throws the following UVM_FATAL message during overriding:
Where, aes_xts_model is the parent class and aes_xts_model_chip is the class derived from aes_xts_model. m_fethrock_env has two instances of sdp UVC, m_sdp_enc_uvc and m_sdp_dec_uvc.
My first concern is the error itself and second one is, why is the error not thrown while overriding the model in m_sdp_enc_uvc.
The way I override base test is:
Please advice.
Thanks,
Vinit
I am trying to integrate a module UVC at chip level. Objective is to pick the uvc from the library. The behavioral model in the UVC requires a project specific hack. After inheriting a new class from the parent class, I make the required changes in the derived class and try to override the same from my base test. It throws the following UVM_FATAL message during overriding:
Code:
UVM_FATAL @ 0: reporter [FCTTYP] Factory did not return a component of type 'aes_xts_model'. A component of type 'aes_xts_model_chip' was returned instead. Name=m_aes_xts_model Parent=sdp_uvc contxt=uvm_test_top.m_fethrock_env.m_sdp_dec_uvcWhere, aes_xts_model is the parent class and aes_xts_model_chip is the class derived from aes_xts_model. m_fethrock_env has two instances of sdp UVC, m_sdp_enc_uvc and m_sdp_dec_uvc.
My first concern is the error itself and second one is, why is the error not thrown while overriding the model in m_sdp_enc_uvc.
The way I override base test is:
Code:
aes_xts_model::type_id::set_type_override(aes_xts_model_chip::get_type());Please advice.
Thanks,
Vinit
