as90
Newbie level 4
Hi,
I've a synthesized netlist with a SPEF and SDC file. My design has some small timing violations. I would like to know if there is a command to optimize timing inside ICC? I'm looking for something like:
read_verilog ...
read_sdc ...
read_parasitics ...
optimize_timing ... # is there a command of this sort
I want to optimize in incremental fashion without much worsening the power.
I'm fine with using DC as well. However, I could not get it to annotate parasitics to my design. Net delays were always 0 inside DC.
Regards
Ankur
I've a synthesized netlist with a SPEF and SDC file. My design has some small timing violations. I would like to know if there is a command to optimize timing inside ICC? I'm looking for something like:
read_verilog ...
read_sdc ...
read_parasitics ...
optimize_timing ... # is there a command of this sort
I want to optimize in incremental fashion without much worsening the power.
I'm fine with using DC as well. However, I could not get it to annotate parasitics to my design. Net delays were always 0 inside DC.
Regards
Ankur