abimann
Member level 4
I use new Artix7 instead of old fpga chip, so I migrate sources to Vivado from ISE so problem is happened.
if like above it says "Error: br_1_4 is not a entity."
if like this, i use work library it said ,"Cannot find <br_1_4> in <library work>. Please ensure that library was compiled, and that a library and a use clause in vhdl file" , it is include in <work> library
How to compile library in Vivado ? or i must open library and write smth but it was working on ISE normally ?
Code:
*************
Library UNISIM;
use UNISIM.vcomponents.all;
use work.library.all;
use work.temp_library.all;
Library XilinxCoreLib;
**********************
component br_1_4
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(3 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(9 downto 0);
doutb: OUT std_logic_VECTOR(3 downto 0));
end component;
begin
bram_01 : entity br_1_4 port map(clka=>clk25, dina=>dataWR, addra=>adrA, wea=>WRENA( 1), clkb=>clk50, addrb=>adrB, doutb=>dataRD( 1));
bram_02 : entity br_1_4 port map(clka=>clk25, dina=>dataWR, addra=>adrA, wea=>WRENA( 2), clkb=>clk50, addrb=>adrB, doutb=>dataRD( 2));
*********
Code:
bram_01 : entity work.br_1_4 port map(clka=>clk25, dina=>dataWR, addra=>adrA, wea=>WRENA( 1), clkb=>clk50, addrb=>adrB, doutb=>dataRD( 1));
bram_02 : entity work.br_1_4 port map(clka=>clk25, dina=>dataWR, addra=>adrA, wea=>WRENA( 2), clkb=>clk50, addrb=>adrB, doutb=>dataRD( 2));
bram_03 : eif like this, i use work library it said ,"Cannot find <br_1_4> in <library work>. Please ensure that library was compiled, and that a library and a use clause in vhdl file" , it is include in <work> library
How to compile library in Vivado ? or i must open library and write smth but it was working on ISE normally ?
