AllenD
Member level 5
Hi team,
Can I please ask 2 simple questions?
My circuit is as follow.
Sorry for the lousy hand drawing
I am using 65nm CMOS technology to design a CMOS current mirror and 2 switches. The first switch is a sample and holds switch, that is used to sample the signal. The seond switch is a discharge switch, which connects a node in the signal path to a constant DC voltage: 0.3V. 0.3V is the neutral voltage of that node when no AC signal is applied. My Vdd is 1.2V. The purpose of that switch is to discharge the caps in my circuit when the switch is on.
Q1: How can I realize the 0.3V DC voltage? I thought about resistive voltage divider( as in option b). But in that case, during the discharge time, the current flow through the resistor will make the voltage created by the voltage divider no longer 0.3V, which will change the on resistance of the discharge switch(Vgs changes)-->RC constant changes--> the percentage of the residue charges is depend on the charges stored in the cap before discharge. That's bad. Or should I connect it to a pad and connect to the outside world(option a)? Can anyone please let me know if there is a better way?
Q2. All of the NMOS current mirrors bulk is connected to the same ground plate. However, I also have 2 NMOS switches as the S/H switch and a discharge switch. These switches are controlled by large rail to rail CLK signals. Should I connect the bulks of these transistors to the same ground or separate?
My intuitive answer is these grounds should be separate because an analog ground should not connect to a digital ground. But the large clock signals already interact with the analog signal through Cgs and Cds of each switch. So does separating their bulk connection still useful? Or even meaningful?
Thanks
Allen
Can I please ask 2 simple questions?
My circuit is as follow.
Sorry for the lousy hand drawing
I am using 65nm CMOS technology to design a CMOS current mirror and 2 switches. The first switch is a sample and holds switch, that is used to sample the signal. The seond switch is a discharge switch, which connects a node in the signal path to a constant DC voltage: 0.3V. 0.3V is the neutral voltage of that node when no AC signal is applied. My Vdd is 1.2V. The purpose of that switch is to discharge the caps in my circuit when the switch is on.
Q1: How can I realize the 0.3V DC voltage? I thought about resistive voltage divider( as in option b). But in that case, during the discharge time, the current flow through the resistor will make the voltage created by the voltage divider no longer 0.3V, which will change the on resistance of the discharge switch(Vgs changes)-->RC constant changes--> the percentage of the residue charges is depend on the charges stored in the cap before discharge. That's bad. Or should I connect it to a pad and connect to the outside world(option a)? Can anyone please let me know if there is a better way?
Q2. All of the NMOS current mirrors bulk is connected to the same ground plate. However, I also have 2 NMOS switches as the S/H switch and a discharge switch. These switches are controlled by large rail to rail CLK signals. Should I connect the bulks of these transistors to the same ground or separate?
My intuitive answer is these grounds should be separate because an analog ground should not connect to a digital ground. But the large clock signals already interact with the analog signal through Cgs and Cds of each switch. So does separating their bulk connection still useful? Or even meaningful?
Thanks
Allen
