jasi
Newbie level 5
I wanted to implement 1 HZ square wave in verilog with out giving system clock signal as input.in which first 500 ms the signal should be high,and remaining 500 ms the clock should be low. i write the delay program by using my logic but clock is always high
my code
anyone please help me .what is the error in this program.or give me logic how to create synthesizable delay of 500 ms .I browsed a lot regarding delay, while doing so I came across a delay formula # num).but it is only for simulation.when approaching to synthesizing this delay formula does not work.
my code
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 module clkgeneration2 (enable,clkout ); input enable; output reg clkout; reg temp; integer a; always@(a) begin for (a=0;a<500;a=a+1) begin if (a<500) temp<= 1'b1; else temp<= 1'b0; end end always@(enable) begin if (enable) clkout<=temp; else clkout<=0; end endmodule
anyone please help me .what is the error in this program.or give me logic how to create synthesizable delay of 500 ms .I browsed a lot regarding delay, while doing so I came across a delay formula # num).but it is only for simulation.when approaching to synthesizing this delay formula does not work.
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