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SystemVerilog assertions in the place of DFT?

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hcu

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Hello,

while i'm reading about sv assertions. i found that these are synthesizable and in silicon too. Makes the debug time lesser.

If this is the case, can we use SVA in place of DFT ?

one more question is, "SVA is used for temporal domain coverage". plz explain this.
I heard about code and functional coverage .
 

Hello,

while i'm reading about sv assertions. i found that these are synthesizable and in silicon too. Makes the debug time lesser.

If this is the case, can we use SVA in place of DFT ?

one more question is, "SVA is used for temporal domain coverage". plz explain this.
I heard about code and functional coverage .

1 - no. very different goals.
2 - weird phrasing. not sure what the author meant. temporal instead of spatial?
 

Design for Test(DFT) is technology used to confirm that a manufactured part is implemented as you instructed. It is used to check manufacturing process failures. It does nothing to check that the instructions meet the requirements of what you were asked to design.

SVA checks that your design satisfies a requirement. e.g. "A request for data must respond within 5 clock cycles" The syntax used with SVA is best suited for protocol checking and state transitions over time - that is called temporal. It is not as well suited for checking validity of data, like a compression algorithm. You will have to write a reference model that predicts what the data should be and checks that by comparing with the actual data. Both SVA and the checkers you write contribute to functional coverage of your requirements.

Code coverage measures whether a test, or a set of tests exercises your RTL code. You can assume that unexercised code is untested or unused functionality, but you cannot assume exercised code is functionally correct.
 
Design for Test(DFT) is technology used to confirm that a manufactured part is implemented as you instructed. It is used to check manufacturing process failures. It does nothing to check that the instructions meet the requirements of what you were asked to design.

SVA checks that your design satisfies a requirement. e.g. "A request for data must respond within 5 clock cycles" The syntax used with SVA is best suited for protocol checking and state transitions over time - that is called temporal. It is not as well suited for checking validity of data, like a compression algorithm. You will have to write a reference model that predicts what the data should be and checks that by comparing with the actual data. Both SVA and the checkers you write contribute to functional coverage of your requirements.

Code coverage measures whether a test, or a set of tests exercises your RTL code. You can assume that unexercised code is untested or unused functionality, but you cannot assume exercised code is functionally correct.

Code:
 It is used to check manufacturing process failures. SVA checks that your design satisfies a requirement.
I thought using sva in the place of LBIST.
whats the purpose of taking SVA into hardware emulation and into the silicon particularly even after verification signoff.
 

Code:
 It is used to check manufacturing process failures. SVA checks that your design satisfies a requirement.
I thought using sva in the place of LBIST.
whats the purpose of taking SVA into hardware emulation and into the silicon particularly even after verification signoff.

for emulation the answer is simple: it runs faster than simulation.
for silicon the answer is fuzzy. the generic answer is no one should be doing it, but I can think about some online monitoring scenarios where it could be a good fit -- still a niche application though.
 
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