Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

I can't find the wrong piece of code for signed calculation in verilog

Status
Not open for further replies.

skyworld_cy

Junior Member level 3
Joined
Jun 29, 2011
Messages
31
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,288
Activity points
1,513
Hi,
I wrote a piece of code to test signed calculation. The code doesn't work as what I expected, I can't find the souce of bug. Can anybody give me some help? thanks.

here is the code:
Code:
 wire  signed [8:0]  sign_a;
  wire  signed [9:0]  constant_a;
  wire  signed [8:0]  result_a;

  assign constant_a = 10'd511;
  assign sign_a = -9'd1;

  assign result_a = (sign_a > constant_a) ? constant_a
                  : (sign_a < 10'd0) ? 9'd0
                  : sign_a;

I assign sign_a to -1. Since -1<0, I expect result_a would be assigned to 0. but after simulation, the result_a is assigned to -1, which confused. Can anybody give me some guide? thnaks.
 

Suggest to read Verilog LRM "11.3.3 Using integer literals in expressions" and "11.8 Expression evaluation rules" to understand how your code is read by the compiler.

I guess that the literals with base specifiers are causing more confusion than being helpful.

- - - Updated - - -

Looking at some details

LRM 11.4.4 Relational operators (...) When one or both operands of a relational expression are unsigned, the expression shall be interpreted as a comparison between unsigned values.

signed [8:0] has a range of -256 to 255, respectively 0 to 511 if interpreted as unsigned value, the comparison (sign_a > 511) is always false and makes no sense either.

Because (sign_a < 10'd0) is performed as unsigned comparison it's false for all negative values. Try (sign_a < 9'sd0) or simply (sign_a < 'sd0) to enforce a signed comparison.
 
Thank you for your kind reply. I will check this.

- - - Updated - - -

Hi FvM,
I have read your post and have one question: sign_a has a range of -256 to 255. This sign_a compares with 10'd511, so both of the operands are unsigned, this means sign_a will be 0x3ff, which is unsigned 1023, it is larger than 10'd511, so the result_a should be 10'd511, right? but simulation result_a isn't that. Could you please help me to find what I missed again? thanks
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top