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Help in simulating ALU with register file

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fadia

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Hello,

I need to design register file that is connected to an ALU in systemverilog, then simulate the top module to verify that operation are performed correctly.

I attached three modules, one for alu, register file, top module, and testbench for top module.


I am having trouble figuring out what to use for the output of the topalu module, since the output of the alu will be fed back to the write data port in register file. Once I figure this out I will figure out the issue with my test bench.

Thanks

Screen Shot 2018-02-03 at 3.47.10 PM.jpg
 

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