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[SOLVED] How I/Os are realized inside FPGA

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mjuneja

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Hello guys

I want to understand how user I/Os pins in FPGA, which can be programmed either as input, output or bidirectional pin in VHDL/Verilog source code; are realized inside FPGA to function either as input or output or bidirectional pin.

Do we have tristate buffer to implement such functions or something else ?

Does it depend on the technology as well ?
 

Hi,

Do we have tristate buffer to implement such functions or something else ?
Click to expand...
Yes.

Does it depend on the technology as well ?
Click to expand...
What exactly do you mean.
There will be tristate buffers in any technology....but for sure the specifications will differ.

Klaus
 
Usually, IO blocks in FPGAs have 4 paths to the physical pin - a direct input, a direct output, a registered output and a tri-state buffer (with enable/high impedance control). The fitter will chose which path is active in any design. All paths will can infered from the HDL code, or controlled via direct instantiation of IO block.

Unless you absolutely need them, you wont use bi-directional buffers. Most pins will be either In our OUt.
 
Usually, IO blocks in FPGAs have 4 paths to the physical pin - a direct input, a direct output, a registered output and a tri-state buffer (with enable/high impedance control).
Click to expand...

That's true in a functional view. Physically, the direct and registered output is through an always enabled tri-state buffer. See a block diagram of Altera Cyclone III IO.

Cyclone III IO.png
 
FvM said:
That's true in a functional view. Physically, the direct and registered output is through an always enabled tri-state buffer. See a block diagram of Altera Cyclone III IO.

View attachment 144317
Click to expand...

From the figure, it seems that for this particular FPGA only the output is tri-stated while the input (whether registered or not) is coming direct only.

So will this scheme remain same for other FPGA's as well ?
 

From the figure, it seems that for this particular FPGA only the output is tri-stated while the input (whether registered or not) is coming direct only.
Click to expand...
I can't think of a reasonable different topology. Should the input be routed through a tri-state buffer? To achieve what particularly?

In fact, all recent FPGA have a similar structure of their general purpose IO pin circuit. The shown diagram is still lacking some details that are usually present
- programmable drive strength, implemented by multiple NMOS and PMOS transistors making the tri-state driver
- additional circuit for differential in- and output standards, connected to many of the IO pins
 

Hi,

So will this scheme remain same for other FPGA's as well ?
Click to expand...

I assume the FPGA is well documented. I recommend to visit the FPGA manufacturer´s internet site. Select your device. Look for technical documentation, especially "I/O" description.

If you follow this ... and don´t find the information within 5 minutes, you should give us the manufacturer name and the exact name of the FPGA.

Klaus
 

KlausST said:
If you follow this ... and don´t find the information within 5 minutes, you should give us the manufacturer name and the exact name of the FPGA.
Click to expand...
... and we will visit them and force them to have better documentation...
 

Hi,

At first we can try to find the informations...

Klaus
 

barry said:
... and we will visit them and force them to have better documentation...
Click to expand...

Hey Barry

Don't drag them to court for not doing proper documentation.:p

Anyway for my FPGA I got the relevant details from their documentation.
 

I recommend using separate "in", "out" and "direction" signals in the design, and only at the top level connect them like this (VHDL):
Code: 
input_signal <= tristate_pin;
if direction_signal = '1' then
  tristate_pin <= output_signal;
else
  tristate_pin <= 'Z';
end if;

This makes it easier to see when the output driver is active in simulation,
and it is the required way to do it in ASIC design, where the I/O-blocks are treated as components (and you don't do the 'Z' assignment).
 

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