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Cadence Encounter: IO Pin shorts

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mcaduser

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Hello,

At the end of my APR, I am getting IO pad short between two pins in one particular metal layer. This happens even after running ECO route and even though this particular location is not metal congested. I'm not sure why this happens. I can fix this manually easily, however I'm trying to come up with an automated way of doing this and would like to understand if there is a tool command or something else I might doing that is causing this short.

I'm attaching a screen capture showing the short of two IO pins both trying in the same metal layer (8) to route pins that are very near each other.

iopin_short.jpg

Thank you for your help.
 

mcaduser said:
Hello,

At the end of my APR, I am getting IO pad short between two pins in one particular metal layer. This happens even after running ECO route and even though this particular location is not metal congested. I'm not sure why this happens. I can fix this manually easily, however I'm trying to come up with an automated way of doing this and would like to understand if there is a tool command or something else I might doing that is causing this short.

I'm attaching a screen capture showing the short of two IO pins both trying in the same metal layer (8) to route pins that are very near each other.

View attachment 144273

Thank you for your help.
Click to expand...

can't really understand what this layout is. Is this block level or chip level? Did you let the tool place the pins for you arbitrarily?
 

ThisIsNotSam said:
can't really understand what this layout is. Is this block level or chip level? Did you let the tool place the pins for you arbitrarily?
Click to expand...

This is at the chip-level. I have some regions blocked out for memories. The blue layer is metal 8, and the highlighted square is one net overlapping with another net, both in metal 8. They are trying to connect to the pins at the boundary (yellow triangle). I don't understand why they are both trying to use metal8, when they could use another metal so there is no short.

Thank you for your help. I am new to using this tool.
 

This is why I am getting confused: if this is chip level, your pins should be your IO cells. The yellow triangle markers are 'logical' pins, but not actual pins. We usually see this yellow markers at block level.

I think you have stumbled into a real DRC but one that will never happen in a realistic scenario with IO cells.
 

Thank you for the clarification. I believe my issue it that I have too many I/O pins for the area needed to fit the standard cells. When the IO pin placement happens based on minimizing routing, this results in congestion in certain areas. If the logical IO pins were spread out more evenly, this congestion would not have corrected, but this might be at the expense of more area needed for the routing.

I am looking for options that I can force the IO pin placement to be spread out. I tried the editPin option after the initial placeDesign, which lets you spread on an edge, but it was not successful. If you have other options that you could suggestion that would help reduce io congestion, at the expense of area, please let me know.

My initial study is focused on the impact of area of blocks, so I'm not worried about the precise placement for IO pins.

Thanks again for all of your help!!
 

mcaduser said:
Thank you for the clarification. I believe my issue it that I have too many I/O pins for the area needed to fit the standard cells. When the IO pin placement happens based on minimizing routing, this results in congestion in certain areas. If the logical IO pins were spread out more evenly, this congestion would not have corrected, but this might be at the expense of more area needed for the routing.

I am looking for options that I can force the IO pin placement to be spread out. I tried the editPin option after the initial placeDesign, which lets you spread on an edge, but it was not successful. If you have other options that you could suggestion that would help reduce io congestion, at the expense of area, please let me know.

My initial study is focused on the impact of area of blocks, so I'm not worried about the precise placement for IO pins.

Thanks again for all of your help!!
Click to expand...

editPin is the right command, just got play with it until you find a configuration that makes sense.
 

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