Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] VHDL Coding for ASIC production (for Newbie)

Status
Not open for further replies.
A

Alexxk

Junior Member level 3
Joined
Jan 31, 2018
Messages
25
Helped
1
Reputation
2
Reaction score
1
Trophy points
3
Activity points
297
Hello guys!

I am an ebedded systems Master student and just started with my master thesis. Its about designing the digital part of a mixed circuit chip. I have experience coding VHDL for FPGA and I was wondering about something when making VHDL code for ASICs: I have access to standart cells from the foundry and I was wondering if I can use them like I use prebuilt blocks in an FPGA: can I just make an instance of an D-FF like I use a BUFG or MUX in a Xilinx FPGA? Is it recommended to do so as much as possible? I will most likely have an asynchronous design and I think it would be better when I can use std. cells and do the glue logic inbetween by myself and not trust the synthesis tools with everything (From my experience with FPGA, tools always want to produce synchronous circuits because thats how FPGAs work). Or does ASIC tools behave in a completly different way?

Thank you for your help!
 

To be noted:
Its about designing the digital part of a mixed circuit chip.
Click to expand...

can I just make an instance of an D-FF like I use a BUFG or MUX in a Xilinx FPGA?
Click to expand...
Why?
Why can't you write RTL code that will infer flops or MUX? Isn't that much easier?
BUFG - Leave it to the PnR guy!

When you are synth your design the std cells will automatically be used by the synth tool.

I will most likely have an asynchronous design and I think it would be better when I can use std. cells...
Click to expand...
I don't think so! In that case also it is recommended to use RTL style design (async logic can also be modeled), unless you are doing something exotic.

If you want to use std_cells every time, I think you are trying to do something like structural modeling rather than behavioral modeling.
 
  • Like
Reactions: Alexxk and FvM

    FvM

    FvM

    Points: 2
    Helpful Answer Positive Rating
    A

    Alexxk

    Points: 2
    Helpful Answer Positive Rating
Thank you for your fast answer!

I will also be the PnR guy for the final chip, the analog parts will be done by someone else though.

What I meant with the instances of BUFG or MUX: Take this asynchronous counter: https://vhsichdl.blogspot.co.at/2013/04/vhdl-code-for-asynchronous-counter.html
Would I feed the exact same code into the synthesis tool, or can I take an available (library) JK-Flipflop use it instead of the coded JK Flip Flop.

The thing is that this is a test chip and the goal is to reduce the area as much as possible, because in the next stage there will be thousands of my design implemented in one chip (I am working on a subpixel and the next stage would be to have have a whole array). But maybe I just dont have enough trust in the design tools because this is my first experience with ASIC design.
 

Not sure if ripple counter is appropriate for your ASIC, but if so, the design tools should have no problems to read a behavioral description.

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

library ieee ;
  use ieee.std_logic_1164.all ;
 
entity ripple_counter is
   port(
    clk     : in  std_logic;
    rst     : in  std_logic;
    q       : out std_logic_vector(3 downto 0)
   );
end ripple_counter;
 
architecture rtl of ripple_counter is
  signal q_i  : std_logic_vector(3 downto 0);
  signal c    : std_logic_vector(3 downto 0);
 
begin
  c <= q(2 downto 0) & clk;
  process(c, rst)
  begin
    if rst = '1' then
      q_i <= (others => '0');
    else
      for i in 0 to 3 loop
        if falling_edge(c(i)) then
          q_i(i) <= not q_i(i);
        end if;
      end loop;
    end if; 
  end process;
  q <= q_i;
end architecture;
 
  • Like
Reactions: Alexxk

    A

    Alexxk

    Points: 2
    Helpful Answer Positive Rating
FPGA tools $3000.00
ASIC synthesis tools $30000.00

FPGA vendors are out to sell parts not tools. Mentor/Cadence/Synopsys/etc sell software tools. If you can perform logic transformations that do a better job than say DC then forget about your Masters degree go get hired by Synopsys!
 
  • Like
Reactions: Alexxk

    A

    Alexxk

    Points: 2
    Helpful Answer Positive Rating
Ok thank you for all your input. I think Ill just be learning by doing and keep thinking on RTL level! Thank you!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top