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Standard Path Delays vs. Critical Path Delays

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msdarvishi

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Dear all,



I have a question that I would sincerely appreciate if someone can provide me a good and resonable definition of that.



We know that we can extract the critical paths in any FPGA design.



My question is that: "What is the difference between "Standard Path Delays" and "Critical Path Delays" in an FPGA design??





Kind replies and help are in advance appreciated.



Regards,
 

critical paths are the ones that are the most likely to fail timing due to excessive number of LUTs between register to register paths. The other paths aren't critical.
 

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