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ISE Does not Recognize Defined Signal

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RosesAreRed

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Okay. So, I was working on a project related to simulation of a PAM modulator. I wrote the MATLAB function and test bench, which was pretty easy. Then, I converted to code to VHDL through HDL Coder in MATLAB in order to simulate it on FPGA. I have access to Spartan 3 model "xc3s400". However, I ran through an error in simulation by misfortune. So, I would appreciate any help in eliminating this error: "HDLParsers:164 Line 40. parse error, unexpected SIGNAL"
By line 40, it means the line I have bolded
Here's the function code:
Code: 
entity PAM_funct is
    Port ( OSR_1 : in  STD_LOGIC;
           Rolloff_1 : in  STD_LOGIC;
           FiltOrder_1 : in  STD_LOGIC;
           Input : in  STD_LOGIC;
           M : in  STD_LOGIC;
           Trans_Flt : out  STD_LOGIC);
end PAM_funct;
-- Signals
  [B]SIGNAL OSR_1_unsigned                   : unsigned(1 DOWNTO 0)[/B];  -- ufix2
  SIGNAL Rolloff_1_unsigned               : unsigned(13 DOWNTO 0);  -- ufix14_En14
  SIGNAL FiltOrder_1_unsigned             : unsigned(6 DOWNTO 0);  -- ufix7
  SIGNAL Input_unsigned                   : vector_of_unsigned4(0 TO 999);  -- ufix4 [1000]
  SIGNAL M_unsigned                       : unsigned(4 DOWNTO 0);  -- ufix5

architecture Behavioral of PAM_funct is
OSR_1_unsigned <= unsigned(OSR_1);
Rolloff_1_unsigned <= unsigned(Rolloff_1);
FiltOrder_1_unsigned <= unsigned(FiltOrder_1);

begin
  outputgen: FOR k IN 0 TO 999 GENERATE
    Input_unsigned(k) <= unsigned(Input(k));
  END GENERATE;
  M_unsigned <= unsigned(M);
Trans_Flt <= '0';
END rtl;

Cheers!
 

signals must be defined inside an architecture, before the begin
signal assignments must occur after the begin of the architecture.
 

TrickyDicky said:
signals must be defined inside an architecture, before the begin
signal assignments must occur after the begin of the architecture.
Click to expand...

Apart from this I can see some more errors in your code.

OSR1 is STD_LOGIC while you are assigning it to OSR1_unsigned which is of size 2 (1 downto 0).
Same is the case with Rolloff_1 which is assigned to Rolloff_1_unsigned of size 14 (13 downto 0), and FiltOrder_1 is also assigned wrongly.

Actually it's better to write VHDL code yourself, MATLAB HDL coder may not be able to generate that efficient code which you can write yourself.
 

mjuneja said:
Apart from this I can see some more errors in your code.

OSR1 is STD_LOGIC while you are assigning it to OSR1_unsigned which is of size 2 (1 downto 0).
Same is the case with Rolloff_1 which is assigned to Rolloff_1_unsigned of size 14 (13 downto 0), and FiltOrder_1 is also assigned wrongly.

Actually it's better to write VHDL code yourself, MATLAB HDL coder may not be able to generate that efficient code which you can write yourself.
Click to expand...

I highly doubt this is from HDL coder, as HDL coder output is normally legal.
 

RosesAreRed said:
You can be assured this is the actual HDL Coder output.
Click to expand...

Quite strange..even the signals are not defined in a standard format.

Some are defined in " downto " and some are in " to ". If you go through some good book on VHDL you can find some good practices to be followed while writing the code.
 

RosesAreRed said:
You can be assured this is the actual HDL Coder output.
Click to expand...

If this is the actual output, there is something wrong with the tool
Are you using the newest tool version? can you try a different version?
If this is the output of HDL coder over several versions, I suggest raising a support ticket with Mathworks as this is very odd behaviour. I never had a similar output.

Quite strange..even the signals are not defined in a standard format.

Some are defined in " downto " and some are in " to ". If you go through some good book on VHDL you can find some good practices to be followed while writing the code.
Click to expand...

Telling people to learn VHDL is not really a valid option. The OP likely has the design in MATLAB and would likely take a lot more time to hand code. HDL coder is not a bad tool, it is just a code-gen tool that most people that write HDL do not like. It is perfectly capable of producing useful designs for FPGAs, do not just put it down.
 

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