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Design of the startup switch

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tisheebird

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Hi Everyone,

I need to design a switch which works such that when we give 1.8 as the control signal which is my input as shown in the picture it should give me -3.6V. and when I give 0 at the input I should get 0 at the output.

Basically I need a configuration as transistors are stacked as shown below in the picture.

This schematic works as input 1.8V then output is 0. When input is 0V out is -3.6V.

I need in opposite way.

Please guide me with the solution.
 

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  • switch.jpg
    switch.jpg
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This schematic works as input 1.8V then output is 0. When input is 0V out is -3.6V.

I need in opposite way.

A trivial solution would be to invert your Pulse signal.
 

A trivial solution would be to invert your Pulse signal.


Thank you for your reply. I have checked with the dc value. But the input will go from 0 to 1.8V in my case.

I need when input is 0 then output should be 0. and when input is 1.8V then output should be -3.6V.
 

Like this?
You need low threshold MOSFETs.
 

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  • Switch.png
    Switch.png
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switch.jpg

This is the schematic i followed. feel free to modify it.

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Like this?switch.jpg
You need low threshold MOSFETs.



I did the design with this schematic which is attached below.
I need to design a switch which works such that when we give 1.8 as the control signal which is my input as shown in the picture it should give me -3.6V. and when I give 0 at the input I should get 0 at the output.

Basically I need a configuration as transistors are stacked as shown below in the picture.
 

I need to design a switch which works such that when we give 1.8 as the control signal which is my input as shown in the picture it should give me -3.6V. and when I give 0 at the input I should get 0 at the output.

Basically I need a configuration as transistors are stacked as shown below in the picture.
Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.
 

Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.

Thank you for your solution. I simulated and it looks fine to me. Could you send me the schematic if instead of -3.6V we want to have -6V. Please send me the schematic in that case.
This needs to be fabricated so just check the breakdown of each transistor incase of -6V.

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Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.

Hello Sir,

I would like to tell you that i checked this schematic and VDS of both the transistors are more that -3.5V which is not okay. CMOS 180nm technology. VDD is 1.8V.

please guide me with the solution.
 

VDS of both the transistors are more that -3.5V which is not okay. CMOS 180nm technology. VDD is 1.8V.

please guide me with the solution.

Does your process offer 5V (I/O) transistors?

BTW: In a bulk CMOS technology (p-substrate) you can't use negative voltages. The p-substrate must be your most negative potential.
 

Does your process offer 5V (I/O) transistors?

BTW: In a bulk CMOS technology (p-substrate) you can't use negative voltages. The p-substrate must be your most negative potential.


No. it offers just 1.8V. I have told you the condition for the switch. But I am really blank somehow.. Could you please suggest me with the solution..
 

If your process offers only transistors which can stand max. 1.8V , it should be clear that you chose the wrong process for your task.

And remember: for bulk p-substrate CMOS processes, the p-substrate must be the most negative potential.

This does not work:
negative_voltage.png
 

If your process offers only transistors which can stand max. 1.8V , it should be clear that you chose the wrong process for your task.

And remember: for bulk p-substrate CMOS processes, the p-substrate must be the most negative potential.

This does not work:
View attachment 144240

I have made the regulated charge pump of -6V and it will be connected to the PWELL region only. But for the startup case, when we power on the chip we want the charge pump should be 0.

I want a switch which works such that output of the switch is 0 when input is 0 and -6V when it is 1.8V.

I have made a switch which works in opposite way.
In this picture shown below let's say the output of the charge pump is -3.6V. When we give 0 then I get -3.6V and when I give 1.8V then output is 0.
switch.jpg

I need same type of switch but in opposite way. Input 0 then output 0. When input 1.8V then output -3.6V.
 

Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.


Could you guide me with an circuit because with the previous circuit when I see the operating point of the transistor then VDS is coming 3.6V which is not realistic. Please I thereby request you...

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Besides being simpler, the circuit I gave achieves what you are specifying, simulate it please and see by yourself.

I am using CMOS 180nm. VDD of 1.8V
 

There are many "1.8V" CMOS flows and I have been
using one that has 5V I/Os and deep trench SOI.

Device stacking works in SOI but fails for reliability
in junction isolated technologies because you cannot
escape the "pinned" body of NMOS relative to gate.
You might find a twin-well technology that can deal
with negative potentials but it may be not much
cheaper than SOI (FEOL added complexity vs starting
material costs).

Very few technologies will be -only- one low core voltage
supply. Maybe memories. ASICs and digital products
have to deal with the wider world and legacy I/O
standards. Therefore most flows -do- offer -some-
I/O device - 5V, 3.3V or 2.5V - capability.

Maybe your teacher has falsely constrained your
choices. Industry only constrains cost vs price.
Breaking constraints (after recognizing them) may
be the object of the lesson. Solving it for you,
surely is not.
 

I need same type of switch but in opposite way. Input 0 then output 0. When input 1.8V then output -3.6V.

If you think you can realize this with your process - you didn't tell if you'd use a p-substrate, an n-substrate or an SOI technology - you could try something like that:

charge-pump-switch.png Note the N3:N4 aspect ratio!
 
you could try something like that
By the way the first comprehensible schematic in this thread, showing input, output, power supply...
 

Basically I need a schematic of the start up circuit for the charge pump during the power on the chip...It cannot be done with 1 single transistor because Vout= -6V. I need a special circuitry which will keep the output of the charge pump close to 0 when supply is off and take -6V when power supply is turned on. My design is a negative 6 stage charge pump....

First schematic is special switch which can give me -6V after 6 stages when pulse signal is 0 and when pulse is 1.8 it will give me 0V. I need similar way but in opposite way...

- - - Updated - - -

By the way the first comprehensible schematic in this thread, showing input, output, power supply...

Basically I need a schematic of the start up circuit for the charge pump during the power on the chip...It cannot be done with 1 single transistor because Vout= -6V. I need a special circuitry which will keep the output of the charge pump close to 0 when supply is off and take -6V when power supply is turned on. My design is a negative 6 stage charge pump....

First schematic is special switch which can give me -6V after 6 stages when pulse signal is 0 and when pulse is 1.8 it will give me 0V. I need similar way but in opposite way...

- - - Updated - - -

If you think you can realize this with your process - you didn't tell if you'd use a p-substrate, an n-substrate or an SOI technology - you could try something like that:

View attachment 144255 Note the N3:N4 aspect ratio!


Basically I need a schematic of the start up circuit for the charge pump during the power on the chip...It cannot be done with 1 single transistor because Vout= -6V. I need a special circuitry which will keep the output of the charge pump close to 0 when supply is off and take -6V when power supply is turned on. My design is a negative 6 stage charge pump....

First schematic is special switch which can give me -6V after 6 stages when pulse signal is 0 and when pulse is 1.8 it will give me 0V. I need similar way but in opposite way...

- - - Updated - - -

If you think you can realize this with your process - you didn't tell if you'd use a p-substrate, an n-substrate or an SOI technology - you could try something like that:

View attachment 144255 Note the N3:N4 aspect ratio!


Thank you I will try this schematic and check.. could you please give me a schematic as if input 0 then output 0, but when input 1.8V output should be -6V ...
Please guide me with the solution
 

could you please give me a schematic as if input 0 then output 0, but when input 1.8V output should be -6V ... Please guide me with the solution

In this case you can renounce on N3, but you need a huge aspect ratio for P1:N4 .

-6V-switch.png

For P1 & N2 you need transistors which can stand at least 8V (and for the others at least 6V , of course). And an SOI process, I'd think.
 

In this case you can renounce on N3, but you need a huge aspect ratio for P1:N4 .

View attachment 144397

For P1 & N2 you need transistors which can stand at least 8V (and for the others at least 6V , of course). And an SOI process, I'd think.


Thanks a lot for this...I agree..But the problem is i am using CMOS 180nm process....1.8V is the max...
please help me with some other circuitry...I am also trying...but ...:(
 

Thanks a lot for this...I agree..But the problem is i am using CMOS 180nm process....1.8V is the max...
please help me with some other circuitry...I am also trying...but ...:(

The problem is ... with a 1.8V process you cannot realize an 8V circuit on the same chip. The same applies for your -6V charge pump. You either need a process which offers min. 8V transistors (perhaps an SOI process with isolated substrates), or you have to realize the -6V charge pump and its switch externally.
 

Thanks a lot for this...I agree..But the problem is i am using CMOS 180nm process....1.8V is the max...
please help me with some other circuitry...I am also trying...but ...:(


The operating points should be 1.8V max for the transistors... more than that it will breakdown and only 1.8V transistors are possible...

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The problem is ... with a 1.8V process you cannot realize an 8V circuit on the same chip. The same applies for your -6V charge pump. You either need a process which offers min. 8V transistors (perhaps an SOI process with isolated substrates), or you have to realize the -6V charge pump and its switch externally.


Okay..But if you see the first schematic it is basically 2 switches for the 2 stage charge pump (-3.6V). The switch is working fine in that..i mean the operating points are less than 1.8V for all the transistors. But I need the same thing in opposite way...

- - - Updated - - -

The problem is ... with a 1.8V process you cannot realize an 8V circuit on the same chip. The same applies for your -6V charge pump. You either need a process which offers min. 8V transistors (perhaps an SOI process with isolated substrates), or you have to realize the -6V charge pump and its switch externally.


I have used 1st schematic(2 stage switch ) in my design as a switch...I have put like this 6 stages inside the charge pump which will hold -6V. It works fine (operating points are less than 1.8V). But now a switch for power on the chip. when there is no supply, the output of the charge pump is 0. and when the supply is ON, then it should give me -6V.
 

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