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Digital circuit to divide larger bits into smaller bits

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mthakur

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can u tell me how can i divide 36 bits into four 9 bits?
means i am having one input of 36 bits and that 36 bits is further divided into four 9 bits and each 9 bits used as address of bram input. so which digital circuit is used to divide?
 

you just want to index. in Verilog, this has a few options. In VHDL, fewer.

Using +: in Verilog
x[0*9 +: 9]; x[1*9 +: 9]; x[2*9 +: 9]; x[3*9 +: 9]; // syntax is x[ base +: width ];

Using : in Verilog
x[(0+1)*9-1 : 0*9]; x[(1+1)*9-1 : 1*9]; x[(2+1)*9-1 : 2*9]; x[(3+1)*9-1 : 3*9]; // syntax is x[high : low];

In VHDL, replace : with downto and [] with (). VHDL does not have +:
 

COuld you better specify what you are doing? are you just trying to slice a bus?
and what language?
 

VHDL doesn't have +: but you can use range types.

siga <= sigb(range)

-----------------

The name for what I believe you want to do it called bit slicing.
The reverse would be bit concatenation.

-----------------

I wouldn't think of it as a digital circuit, rather just bundling wires(signals) together.
Code VHDL - [expand]
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type rangeA is range 8 downto 0;
type rangeB is range 17 downto 9;
--
AddressA <= in32bit(rangeA);
AddressB <= in32bit(rangeA);
AddressC <= in32bit(rangeA);
AddressD <= in32bit(rangeA);
-- instantiation of bram
 addrA => AddressA,
 data   => x,
 

wesleytaylor said:
VHDL doesn't have +: but you can use range types.
Click to expand...

There is no such thing as a range type.

In your example, the rangeA and rangeB are just integer types. And an integer type cannot be used to define a range directly. You would need to use 'high and 'low (or 'left and 'right). 'range is only applicable to an array type.

AddressA <= in32bit(rangeA'high downto rangeA'low);

VHDL2008 makes life a little easier with the addition of 'subtype and 'element, that allow easy definition of objects, especially in things like processes and functions where lengths may be unconstrained in the code:

Code: 
signal a : ip'subtype;
signal b : array_ip'element;
 
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IIRC, you would need to use subtypes. VHDL does allow:
Code: 
subtype my_range is natural 15 downto 8;
signal my_signal : std_logic_vector(my_range);
...
y <= x(myrange); -- indexing for assignments too.
z(my_range) <= y;

--edit, maybe "type" also works. I don't think I've ever tried it after seeing that subtype worked, and was a bit more clear.
 

type does not work (tried). But yes subtype is allowed.

But we are offering solutions to a problem that may not exist. Why has no one suggested just using literals to slice the array?

Code: 
op0 <= ip(8 downto 0);
op1 <= ip(17 downto 9);
--etc

or in verilog:
Code: 
op1 <= ip[8:0];
op2 <= ip[17:9];
//etc
 

if you can't bitslice some array of bits then you are really lost. forget about implementing the architecture from this paper, go read some verilog/vhdl tutorial. this is REALLY basic.
 

IEEE documents are behind a paywall. Links to them are useless for the majority of forum members.
 

I did have a look at this document. This is not a simple exercise for someone with your apparent level of Verilog knowledge. This is an implementation of scalable parallel ternary CAMs, and Figure 3 is only a vast simplification of the actual block you would have to deliver. Figure 4 below it shows more of the complexity involved. This is NOT trivial. As has been pointed out above, if splitting up a bus is outside of your level of knowledge, then you will not succeed in implementing this without getting some ability in Verilog.

I've been doing this stuff for a long time and I think it would take me at least two weeks to wade through all the math, write the HDL, write a testbench and then simulate it.

Not a good choice at all for a first project.

r.b.
 

i already completed half portion.. i made that ram part and its reading and writing the stored value and i divided the bits in sub-bits.its not dat tough to divide. but now i have to connect that with BRAM.. and how tcam will work with that bram searches? i think i should use comparator to compare all of the 8 bits wiith stored value in RAM. can u suggest me? please if u are able to do then please help me.
 

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