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[SOLVED] Gated reset for register

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mjuneja

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Code: 
process(rst,clk,x,z)
begin
	if ((rst = '0') or (z = '1')) then
		y <= '0';
	elsif(rising_edge(clk)) then
		if(x = '1') then
		     y <= '1';
		end if;	
	end if;
end process;

In the above shared VHDL code for defining a register, 'rst' is the global reset for the whole circuit and 'clk' is the global clock.

My query is regarding usage of gated reset for defining register that whether

1. It is a good practice to use gated reset as I have shown in the code ?

2. What are the implications of using gated resets (if any) ?

please share some insights over it
 

Hi,

In my eyes a gated RST makes no sense. A RST should work without the influence of any other signal.
What is it good for?

Klaus
 
having async resets that are used during normal operation complicates things.

A large issue is glitches. For example, if z = a and b in your above example, the expression could be true if a is transitioning from 1 to 0 and b is transitioning from 0 to 1. There might be overlap and possibly a reset. if this is used for a reset of a bus, it is possible routing issues will result in the reset being accepted by some registers and rejected by others.

Overall, it isn't ideal. If the reset is driven from a register in the same clock domain this wouldn't be an issue, but at that point there might not be a need for it to be async anyways. (this can also create longest-paths that are based on the routing to the async reset then through the FF to the next FF layer.)

Because the style is possibly error prone, I would avoid writing code in this way. When weird code looks weird, it makes it easier to identify.
 
There's no gating operation involved, it's an OR operation. Presuming RST (actually nRST in the shown logic) is a power-on or global reset, what's the purpose of another asynchronous reset?

An asynchronous reset must be synchronously released to avoid timing violations and unpredictable behavior, there's little room for non-global asynchronous reset operations in usual synchronous logic design.

And as KlausST mentioned, gating a global reset would be just useless.
 

KlausST said:
Hi,

In my eyes a gated RST makes no sense. A RST should work without the influence of any other signal.
What is it good for?

Klaus
Click to expand...

Actually in my logic active high signal 'x' can make signal 'y' as high but to make 'x' again low I need the help of signal 'z' that's why thought of this solution.
 

I don't want to repeat what others have mentioned about the usage of a reset signal.

Actually in my logic active high signal 'x' can make signal 'y' as high but to make 'x' again low I need the help of signal 'z' that's why thought of this solution.
Click to expand...

Having said that, look here:
process(rst,clk,x,z)

In makes sense to put signals in the sensitivity list which are async to the clk signal. A global rst signal always finds its place here.

Now coming to your statement, you have given us no info as to the source/use of signals x and y.
You code snippet tell me that x and z are async to clk.
A usual approach is to make the signal x sync to clk domain and then use it.
 

Just providing you some more info about the signals used in my code.

only rst is the asynchronous signal and that too will be used only for power on reset,
rest of the signals viz. x and z are already sync to clk.

So is it a good idea to OR rst and z asynchronously to make y '0' ?
 

It will depend on technology.
Altera - Should be fine, as all regs are async reset. Their recommendation though is that ALL resets are async asserted, and sync de-asserted. Synchronous resets can be emulated in logic though.
Xilinx. They have a GSR reset, that is fanned out everywhere. This should be the power on reset. Z should be connected to the sreset port of the registers (as they otherwise dont have an async register)

So I think your questions seems a little odd. You can easily do what you're doing. But why bother?
 

Lmftfy

There are multiple ways of restructuring the code to each have different outputs.
Basically what we have below is
y shall be 0 on reset. y shall only update to '1' when x is true. Once updated y stays '1'
y shall be 0 when z is true and shall stay so until explicitly told otherwise.
Code VHDL - [expand]
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process(rst,clk,x)
begin
    if (rst = '0') then
        y <= '0';
    elsif(rising_edge(clk)) then
        if(x = '1') then
             y <= '1';
        end if;
                if (z = '1') then
                     y <= '0';
                end if; 
    end if;
end process;


This is making us of a latching enable 'x' or a clear 'z'
 

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