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[SOLVED] Malfunctioning of a shift register implemete as a Moore-Type state machine

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Igor_Kh

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Hello,

I am trying to implement a shift register in the concept of Moore-Type state machine. The implementation I have developed produces incorrect result in "Shift data left" state.

The problem is that on the signal to shift data left (shlf) the content of the register ("register_content") in is not shifted left bit by bit on each clock signal, but rather all register bits are updated with the value on the serial input ("si") during one cycle. The functionality of the shift circuit description

Code VHDL - [expand]
1
register_content <= register_content(SHIFT_REGISTER_WIDTH - 2 downto 0 & si when SHIFT_DATA_LEFT


beyond the concept of the state machine was tested and it works well.

The complete code of the state machine is synthesizable and the synthesized RTL schematic looks correct in my opinion. I am a newbie in digital design and got stuck at this point, please give me a hint on that.

Here below are the complete code, functional wave diagram for the case and RTL view schematic. The tool used for simulation is the ModelSim PE Student Editionn 10.4.


Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity shift_register is
    generic(
            SHIFT_REGISTER_WIDTH : integer := 24
        );
    
    port(
         rst  : in std_logic;
         clk  : in std_logic;
         shlf : in std_logic;     -- command: shift left
                 ld    : in std_logic;  -- command: load parallel data
         d  : in  std_logic_vector(SHIFT_REGISTER_WIDTH - 1 downto 0);
         si   : in std_logic;   -- data serial input in shift left mode
         q    : out std_logic_vector(SHIFT_REGISTER_WIDTH - 1 downto 0)
         );
end shift_register;
 
architecture behavioural of shift_register is
    type state is(IDLE, LOAD_DATA, SHIFT_DATA_LEFT, RESET);
    
    signal pr_state     : state;    -- present state
    signal nx_state     : state;    -- next state
    signal register_content : std_logic_vector(SHIFT_REGISTER_WIDTH - 1 downto 0);
 
begin
    next_state_combinational_logic:
    process
    begin
        wait on rst, shlf, ld;
        case pr_state is
        when IDLE =>
            if(rst = '1')then
                nx_state <= RESET;
            elsif(shlf = '1')then
                nx_state <= SHIFT_DATA_LEFT;
            elsif(ld = '1')then
                nx_state <= LOAD_DATA;
            else
                nx_state <= IDLE;
            end if;
                
        when RESET =>
            if(rst = '0')then
                nx_state <= IDLE;
            else
                nx_state <= RESET;
            end if;
 
        when LOAD_DATA =>
        
            if(ld = '0')then
                nx_state <= IDLE;
            else
                nx_state <= LOAD_DATA;
            end if;
            
        when SHIFT_DATA_LEFT =>
        
            if(shlf = '0')then
                nx_state <= IDLE;
            else
                nx_state <= SHIFT_DATA_LEFT;
            end if;
        
        end case;
    end process;
    
    output_value_logic: block
    begin
        with pr_state select
            register_content <= register_content when IDLE,
                       (others => '0')when RESET,
                       (register_content(SHIFT_REGISTER_WIDTH - 2 downto 0) & si) when SHIFT_DATA_LEFT,
                       d when LOAD_DATA;
                   
        
        with pr_state select
            q <= register_content when IDLE,
                register_content when RESET,
                register_content when SHIFT_DATA_LEFT,
                register_content when LOAD_DATA;
                 
    
    end block output_value_logic;
                
    state_register_logic:
    process
    begin
        wait on clk;
        if(falling_edge(clk))then
            pr_state <= nx_state;
        end if;
    end process;
    
end behavioural;


Wave.pngStatemachine.PNG

Best regards,
Igor
 

I find some serious errors in your code. Here is my observation:-

1. You have not declared your register_content as "register" which should be clock driven, that's why it is forming a latch in your RTL schematic.
Code:
output_value_logic: block
    begin
        with pr_state select
            register_content <= register_content when IDLE,
                       (others => '0')when RESET,
                       (register_content(SHIFT_REGISTER_WIDTH - 2 downto 0) & si) when SHIFT_DATA_LEFT,
                       d when LOAD_DATA;
                   
        
        with pr_state select
            q <= register_content when IDLE,
                register_content when RESET,
                register_content when SHIFT_DATA_LEFT,
                register_content when LOAD_DATA;
                 
    
    end block output_value_logic;
should have clock in the sensitivity list, so that it should update at every falling/rising edge of clock cycle and since you are using falling edge for state register I would recommend you to use the same edge for this register as well.

2. For shifting register by 1 bit you cannot make "shlf" active high for more than 1 clock cycle as it can be seen in the waveform diagram that it is active for 3 clock cycles.
 

    V

    Points: 2
    Helpful Answer Positive Rating
Your FSM code is... nasty. Google (and adhere to) the commonly used templates.
 

    V

    Points: 2
    Helpful Answer Positive Rating
The main issue here is lack of clock on the register.
Also wondering what you used to learn vhdl. Using wait on at the start of processes, and blocks are not generally used.
 

Yes, that is exactly the point), I am learning vhdl and try to discover it for myself as much as I wish. Since the FSM template I used was confusing me, particularly for this application, I decided to try to use it in such a way. Now, I have the feelings of the pros and cons).
 

I would recommend you to please go through this book for better code writing.

"RTL_Hardware_Design_Using_VHDL by Pong P. Chu.
 

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