I
Igor_Kh
Guest
Hello,
I am trying to implement a shift register in the concept of Moore-Type state machine. The implementation I have developed produces incorrect result in "Shift data left" state.
The problem is that on the signal to shift data left (shlf) the content of the register ("register_content") in is not shifted left bit by bit on each clock signal, but rather all register bits are updated with the value on the serial input ("si") during one cycle. The functionality of the shift circuit description
beyond the concept of the state machine was tested and it works well.
The complete code of the state machine is synthesizable and the synthesized RTL schematic looks correct in my opinion. I am a newbie in digital design and got stuck at this point, please give me a hint on that.
Here below are the complete code, functional wave diagram for the case and RTL view schematic. The tool used for simulation is the ModelSim PE Student Editionn 10.4.
Best regards,
Igor
I am trying to implement a shift register in the concept of Moore-Type state machine. The implementation I have developed produces incorrect result in "Shift data left" state.
The problem is that on the signal to shift data left (shlf) the content of the register ("register_content") in is not shifted left bit by bit on each clock signal, but rather all register bits are updated with the value on the serial input ("si") during one cycle. The functionality of the shift circuit description
Code VHDL - [expand] 1 register_content <= register_content(SHIFT_REGISTER_WIDTH - 2 downto 0 & si when SHIFT_DATA_LEFT
beyond the concept of the state machine was tested and it works well.
The complete code of the state machine is synthesizable and the synthesized RTL schematic looks correct in my opinion. I am a newbie in digital design and got stuck at this point, please give me a hint on that.
Here below are the complete code, functional wave diagram for the case and RTL view schematic. The tool used for simulation is the ModelSim PE Student Editionn 10.4.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity shift_register is generic( SHIFT_REGISTER_WIDTH : integer := 24 ); port( rst : in std_logic; clk : in std_logic; shlf : in std_logic; -- command: shift left ld : in std_logic; -- command: load parallel data d : in std_logic_vector(SHIFT_REGISTER_WIDTH - 1 downto 0); si : in std_logic; -- data serial input in shift left mode q : out std_logic_vector(SHIFT_REGISTER_WIDTH - 1 downto 0) ); end shift_register; architecture behavioural of shift_register is type state is(IDLE, LOAD_DATA, SHIFT_DATA_LEFT, RESET); signal pr_state : state; -- present state signal nx_state : state; -- next state signal register_content : std_logic_vector(SHIFT_REGISTER_WIDTH - 1 downto 0); begin next_state_combinational_logic: process begin wait on rst, shlf, ld; case pr_state is when IDLE => if(rst = '1')then nx_state <= RESET; elsif(shlf = '1')then nx_state <= SHIFT_DATA_LEFT; elsif(ld = '1')then nx_state <= LOAD_DATA; else nx_state <= IDLE; end if; when RESET => if(rst = '0')then nx_state <= IDLE; else nx_state <= RESET; end if; when LOAD_DATA => if(ld = '0')then nx_state <= IDLE; else nx_state <= LOAD_DATA; end if; when SHIFT_DATA_LEFT => if(shlf = '0')then nx_state <= IDLE; else nx_state <= SHIFT_DATA_LEFT; end if; end case; end process; output_value_logic: block begin with pr_state select register_content <= register_content when IDLE, (others => '0')when RESET, (register_content(SHIFT_REGISTER_WIDTH - 2 downto 0) & si) when SHIFT_DATA_LEFT, d when LOAD_DATA; with pr_state select q <= register_content when IDLE, register_content when RESET, register_content when SHIFT_DATA_LEFT, register_content when LOAD_DATA; end block output_value_logic; state_register_logic: process begin wait on clk; if(falling_edge(clk))then pr_state <= nx_state; end if; end process; end behavioural;
Best regards,
Igor