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Questions on PCIE communication protocol implementation in RIFFA

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promach

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I have some questions on https://sites.google.com/a/eng.ucsd.edu/matt-jacobsen/riffa/riffa_2_0/hw-interface

Screenshot from 2018-01-24 19-16-47.png Screenshot from 2018-01-24 19-17-01.png Screenshot from 2018-01-24 19-17-08.png

1) why does CHNL_RX have to align with deassertion of CHNL_RX_DATA_VALID while CHNL_TX does not have to ?

2) CHNL_RX signal will remain high until all data for the transaction has been received into the FIFO. <-- how does it know this from FIFO full signal ?

3) For the following verilog code,
a) why is CHNL_RX_DATA_REN used as output while CHNL_TX_DATA_REN used as input ?​
b) what is the purpose of #1 delay in the context of the FSM below ?​



Code Verilog - [expand]
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// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
// 
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// 
//     * Redistributions of source code must retain the above copyright
//       notice, this list of conditions and the following disclaimer.
// 
//     * Redistributions in binary form must reproduce the above
//       copyright notice, this list of conditions and the following
//       disclaimer in the documentation and/or other materials provided
//       with the distribution.
// 
//     * Neither the name of The Regents of the University of California
//       nor the names of its contributors may be used to endorse or
//       promote products derived from this software without specific
//       prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename:            chnl_tester.v
// Version:             1.00.a
// Verilog Standard:    Verilog-2001
// Description:         Sample RIFFA channel user module. Designed to exercise
//                      the RIFFA TX and RX interfaces. Receives data on the
//                      RX interface and saves the last value received. Sends
//                      the same amount of data back on the TX interface. The
//                      returned data starts with the last value received, 
//                      resets and increments to end with a value equal to the
//                      number of (4 byte) words sent back on the TX interface.
// Author:              Matt Jacobsen
// History:             @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module chnl_tester #(
    parameter C_PCI_DATA_WIDTH = 9'd32
)
(
    input CLK,
    input RST,
    output CHNL_RX_CLK, 
    input CHNL_RX, 
    output CHNL_RX_ACK, 
    input CHNL_RX_LAST, 
    input [31:0] CHNL_RX_LEN, 
    input [30:0] CHNL_RX_OFF, 
    input [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA, 
    input CHNL_RX_DATA_VALID, 
    output CHNL_RX_DATA_REN,
    
    output CHNL_TX_CLK, 
    output CHNL_TX, 
    input CHNL_TX_ACK, 
    output CHNL_TX_LAST, 
    output [31:0] CHNL_TX_LEN, 
    output [30:0] CHNL_TX_OFF, 
    output [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA, 
    output CHNL_TX_DATA_VALID, 
    input CHNL_TX_DATA_REN
);
 
reg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'b0}};
reg [31:0] rLen=0;
reg [31:0] rCount=0;
reg [1:0] rState=0;
 
assign CHNL_RX_CLK = CLK;
assign CHNL_RX_ACK = (rState == 2'd1);
assign CHNL_RX_DATA_REN = (rState == 2'd1);
 
assign CHNL_TX_CLK = CLK;
assign CHNL_TX = (rState == 2'd3);
assign CHNL_TX_LAST = 1'd1;
assign CHNL_TX_LEN = rLen; // in words
assign CHNL_TX_OFF = 0;
assign CHNL_TX_DATA = rData;
assign CHNL_TX_DATA_VALID = (rState == 2'd3);
 
always @(posedge CLK or posedge RST) begin
    if (RST) begin
        rLen <= #1 0;
        rCount <= #1 0;
        rState <= #1 0;
        rData <= #1 0;
    end
    else begin
        case (rState)
        
        2'd0: begin // Wait for start of RX, save length
            if (CHNL_RX) begin
                rLen <= #1 CHNL_RX_LEN;
                rCount <= #1 0;
                rState <= #1 2'd1;
            end
        end
        
        2'd1: begin // Wait for last data in RX, save value
            if (CHNL_RX_DATA_VALID) begin
                rData <= #1 CHNL_RX_DATA;
                rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);
            end
            if (rCount >= rLen)
                rState <= #1 2'd2;
        end
 
        2'd2: begin // Prepare for TX
            rCount <= #1 (C_PCI_DATA_WIDTH/32);
            rState <= #1 2'd3;
        end
 
        2'd3: begin // Start TX with save length and data value
            if (CHNL_TX_DATA_REN & CHNL_TX_DATA_VALID) begin
                rData <= #1 {rCount + 4, rCount + 3, rCount + 2, rCount + 1};
                rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);
                if (rCount >= rLen)
                    rState <= #1 2'd0;
            end
        end
        
        endcase
    end
end
 
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
    .CONTROL0(wControl0)
);
 
chipscope_ila_t8_512 a0(
    .CLK(CLK), 
    .CONTROL(wControl0), 
    .TRIG0({3'd0, (rCount >= 800), CHNL_RX, CHNL_RX_DATA_VALID, rState}),
    .DATA({442'd0,
            CHNL_TX_DATA_REN, // 1
            CHNL_TX_ACK, // 1
            CHNL_RX_DATA, // 64
            CHNL_RX_DATA_VALID, // 1
            CHNL_RX, // 1
            rState}) // 2
);
*/
 
endmodule

 

1) According to the completion TLP in https://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1 , why https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/recv_credit_flow_ctrl.v#L65-L68 allocated 12 bits and 8 bits for data and header respectively ?

Completion_TLP.png

2) For **broken link removed** , why " Note that data on CHNL_RX_DATA may begin to arrive before CHNL_RX_ACK is pulsed, but the FIFO will never overflow. " ?

3) Why https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/tx_port_channel_gate_32.v#L109-L124 and https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/rx_port_32.v#L247-L286 using different number and types of FIFO ?
 

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