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hello everyone
Iam using PSOC . PSOC board support verilog. i wanted to implement clock generator in this board. anyone please help me .how to implement this .
i wanted to implement i2c communication with psoc by using verilog . As a part of this i wanted to generate SCL clocks signal . i know SCL timing diagram and also what changes happened to reading and writing operation on SCL . how to implement SCL signals by using this data . If anyone knows logic please give me idea .
All you need is a counter to generate an "enable" signal to control a toggle FF .... it's output is the SCL.
There is more than plenty of code in the internet on how to do this.
Also - I'm sure - there are complete I2C codes available.
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You have to consider if you want to implement "SCL stretching by an I2C slave".
This is a bit more complicated, because you need to take care about the true SCL state of the bus
..and you need to consider how to timeout this situation.
An I2C interface implemented in programmable logic will usually generate all required timings by dividing down the system clock, creating clock enables with specific rate.
Can you mention the used PSoC device to give us an idea of the available logic resources?
Afaik, the PSOC3 is a registered trademark belonging to Cypress, composed of a CPU and a SOC (analog+digital) on the same chip, and in this architecture - based on the core 51 - already has an I2C peripheral built into the CPU itself, no need to waste extra resources on that. Considering that this is a bus that can be shared among devices, are you sure you're really needing another I2C interface ?
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