SDF file - Propagation delay of cell changes throughout implementation

Hello everyone,

I have encountered this rather strange behaviour when writing .sdf files ( and simulating the corresponding netlist ).
After placement step, the sdf file contains the following delays for a given path ( a flip flop ) :

1) clock pin to flip flop's clock input : 6ps delay ( interconnect delay )
2) flip flop's clock to Q delay : 92 ps delay ( propagation delay )
3)flip flop's Q to output pin : 1 ps delay ( interconnect )
So a total of 99 ps delay from clock pin to output pin

So far so good, as according to the documentation for the given load the propagation delay should be 92 ps.

After routing though ( and CTS ) the propagation delay of the same flip flop is now 99ps!
It seems like the interconnect delays are added up and incorporated in the propagation delay of the cell.
Why does this happen? Is there an option that i must add?

Thank you in advance,
Nikos

CLK->Q delay is proportional to the slew/load, it is expected to change. Am I missing something?

But the load at the output pin of the flip flop does not change!
It seems like it adds up the interconnection delays to the propagation delay of the cell, and in the next step of the implementation the tool uses the sum of ( interconnection + propagation ) delay as the new propagation delay of the cell.

From pre to post route the extraction effort is expected to change. Maybe that is what you are seeing.

Thank you for your answer.
Its just strange because it keeps all the delay from interconnections from the placement phase even though these interconnections change during routing due to buffer insertion