Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Synthesis and STA with multiple SDC files

Status
Not open for further replies.

ebuddy

Full Member level 3
Joined
May 15, 2007
Messages
177
Helped
35
Reputation
70
Reaction score
34
Trophy points
1,308
Activity points
2,372
Hi,

It is a common practice to have separate SDC constraint files for functional mode and scan mode during ASIC synthesis and static timing analysis.

Just curious why that is the case? So in scan mode SDC, we need to do :
1. create_clock for scan clock; this scan clock usually has low frequency than the function clock
2. set_input_delay and set_output_delay for scan_in, scan_out, scan_en.
3. set_case_analysis to enable scan_mode

Is it because we have the set_case_analysis and we have to put that in a separate SDC file?

Any comments?

Regards,

ebuddy
 

when you create the corners for the tool you have to associate sdc files to them. one file would have set_case_analysis 0, the other would have set_case_analysis 1. you can't get this functionality from a single file.
 

when you create the corners for the tool you have to associate sdc files to them. one file would have set_case_analysis 0, the other would have set_case_analysis 1. you can't get this functionality from a single file.


Thanks for the explanation. Please allow me to dig a little deeper.

Why do we use "set_case_analysis" to deal with scan mode? There could be many function modes in the design, and yet we don't use “set_case_analysis" to separate these modes into different sdc files, yet for scan mode, we do. In other words, can scan mode be treated as another functional mode? why not?

Another related question: for a design using multiple sdc files, how do we close the timing simultaneously? let's say we use function sdc to synthesize and meet timing, but when we do STA using scan mode sdc, and there are violations, what are we going to do?

Thanks a lot,

ebuddy
 

your first question is too broad. we use it because it works. there are scenarios where you will use set_case_analysis for things other than scan. I am taping out a design right now that has 4 functional corners and a couple of case analysis statements for some "enable" signals.

"closing time with multiple sdcs" is technically not correct. you close timing on multiple corners, functional or process corners, which may or may not include multiple sdcs. as long as you have all the corners you care about set to active, the tools will work on ALL of them at the same time.
 

your first question is too broad. we use it because it works. there are scenarios where you will use set_case_analysis for things other than scan. I am taping out a design right now that has 4 functional corners and a couple of case analysis statements for some "enable" signals.

"closing time with multiple sdcs" is technically not correct. you close timing on multiple corners, functional or process corners, which may or may not include multiple sdcs. as long as you have all the corners you care about set to active, the tools will work on ALL of them at the same time.

your first question is too broad. we use it because it works. there are scenarios where you will use set_case_analysis for things other than scan. I am taping out a design right now that has 4 functional corners and a couple of case analysis statements for some "enable" signals.

"closing time with multiple sdcs" is technically not correct. you close timing on multiple corners, functional or process corners, which may or may not include multiple sdcs. as long as you have all the corners you care about set to active, the tools will work on ALL of them at the same time.

Hi !Sam,

It is very helpful to get your insight of this subject.

So I create 2 sdc files, func.sdc and scan.sdc, with set_case_analysis disable/enable scan mode, then I do
create_constraint_mode -sdc_files {func.sdc scan.sdc} -name cmode
then:
create_analysis_view -name av1 -constraint_mode cmode -delay_corner xxx
then
set_analysis_view -setup {av1} -hold {av2}

this is how I pass 2 sdc files to the tool and let it do the optimization. Sounds right?

Thanks,

ebuddy
 

almost. remember that you have to pass hold and setup on every case. so it should be like:

Code:
create_constraint_mode -sdc_files {func.sdc } -name func_mode
create_constraint_mode -sdc_files {test.sdc } -name test_mode

create_analysis_view -name av_func -constraint_mode func_mode -delay_corner xxx
create_analysis_view -name av_test -constraint_mode test_mode -delay_corner xxx

set_analysis_view -setup {av_func av_test} -hold {av_func av_test}
 

Very good. Thanks a lot.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top