Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to reduce input referred noise in cadence

Status
Not open for further replies.
I

ICdesignerbeginner

Member level 5
Joined
Nov 22, 2017
Messages
86
Helped
1
Reputation
4
Reaction score
2
Trophy points
8
Activity points
729
Hi

can some one help me in reducing the input referred noise. I have simulated input referred noise in cadence but I am getting high input referred noise due to only 2 transistors. I increased the size of the transistor generating noise but still my noise has not reduced. The noise got reduced in the noisy transistor by increasing the sizes but the other transistor noise have increased it means the noise from the noisy transistor has been shifted to other transistors by increase in sizes and the overall input referred noise remained same. How to reduce input referred noise.
 

Input referred noise is the output noise divided down by the power gain of the circuit. Thus if you decrease noise of a device, it can decrease the power gain and your input referred noise can be the same.
Noise can't shift from one to other device. Only contribution percentage can be increased of an other device.
ICdesignerbeginner said:
How to reduce input referred noise.
Click to expand...
There are wide choice of sources, books on the internet to answer this not specific "question". You didn't show any information about your circuit. This is a forum not a school.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top