Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

increase no'of multipliers vs VDD

Status
Not open for further replies.

circuitking

Full Member level 5
Joined
Jan 8, 2018
Messages
291
Helped
1
Reputation
2
Reaction score
1
Trophy points
18
Activity points
2,503
If I increase the number of multipliers term in a transistor,show I also increase VDD that many times? or is it going to taken care? because all the transistors are in parallel and they all going to have same VDD
 
Last edited by a moderator:

Are you referring to a signal amplifier with multi stage transistors ? What should actually be done is an analysis of the whole power dissipated against the power delivered on output, or in other words, to calculate the efficiency of the system. There is no generic answer, but in general the last stage is what practically which determines that value.
 

"multipliers term" means cascaded amplifier ??

If possible can you please share the schematic.

Attached transistor properties screen

Multiplier.png
 

As you did not post to the ASIC section, in addition to the question being not sufficient elaborated this led people to a wrong premise that you were referring to the design of analog circuits.

Thread moved
 

I am asking about the "multiplier" option in transistor properties in cadence.

The multiplier (m) creates m parallel devices with the same properties. This has nothing to do with VDD.
Here an example for an m=3 NMOS. In the netlist shown as (e.g.) M<1:3>

m-multiplier.png
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top