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I/O pin FPGA voltage level translation for interfacing

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fpga93

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Hi all,

I have recently encountered a problem while working with a design that has alot (4 to 5) 3.3 v I/O peripherals to be interfaced with Cyclone 10 GX FPGA. The design challenge is the FPGA has just 48 pins (1 I/O ) bank that supports I/O standards upto 3.3 V ,rest all pins among the other 280+ pins are supporting standards only upto 1.8 V .

One of the 3.3V peripherals itself have around 60-70 I/O pins , using a voltage translator chips might introduce skew between the signals...as voltage translator chips generally only support max upto 32 signals.

If anyone can suggest a workaround to effectively use Cyclone 10 GX smoothly.

Thanks,
fpga993
 

What is the frequency of signals running between FPGA and these peripherals ?
 

The FPGA has to support a 66 Mhz PCI block which itself accounts to more than 48 pins (60 plus)..we cannot employ multiple voltage translator chips dividing these signals to groups as skew may arise...
 

Too much speculation, too little actual specification. Fast level translators have propagation delays down to 2 ns, much better than required for PCI.

There's no workaround. Either use a FPGA family that natively supports 3.3V PCI or suitable level translators.
 

In terms of pin utilization, a PCIe to PCI bridge would be the best solution.
 
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    fpga93

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Oh you mean to include an external PCIe to PCI bridge chip solution,so that the number of PCIe signals coming from/to fpga is few and also effectively my PCI device is supported.(correct me if my understanding is wrong as i am a beginner ..)
That would be a great solution :)
 

Hi all,

One of the 3.3V peripherals itself have around 60-70 I/O pins , using a voltage translator chips might introduce skew between the signals...as voltage translator chips generally only support max upto 32 signals.
fpga993

Looking at the details, it seems voltage translator is a must here.
However if you are suspecting any significant skew between signals coming from 2 translator chips; that can be corrected by using synchroniser for these 2 set of signals withing FPGA. So that all your incoming signals will get synchronized to a common clock.
 
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    fpga93

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Oh you mean to include an external PCIe to PCI bridge chip solution,so that the number of PCIe signals coming from/to fpga is few and also effectively my PCI device is supported.(correct me if my understanding is wrong as i am a beginner ..)
That would be a great solution :)
Something like these or some other vendor's version would probably suffice.
https://www.idt.com/products/interface-connectivity/pci-express-solutions/pci-express-bridges/?field-primary-pci-bus=PCIe+x1&method-field-primary-pci-bus=OR&field-transparency-mode=Transparent&method-field-transparency-mode=OR

Though it means you will need giga-bit transceivers on your FPGA to connect to the PCIe of the bridge device. Hopefully the FPGA device you selected has the transceivers and there is a PCIe core that you can get from the FPGA vendor.

- - - Updated - - -

Looks like the Cyclone 10 GX does have transceivers and has support for PCIe (a core?), it looks like the dev kit for PCIe was supposed to be released this month. you might want to check with your Intel FAE.
 
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    fpga93

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