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    How to create a controlled delay in clock generator circuit

    Hello team
    I am trying to build a clock generator in CMOS circuit. The clock generator circuit has one ideal input clock and will output several clocks of different phases, duty cycles and period, which is desired by my switched capacitor circuit clock. The clock generator was designed based on Johnson counter.

    I have one problem. There is a little phase error between 2 of the output clocks from the clock generator. I believe the phase error was due to the parasitics in the clock generator (the clock freq is pushing to the limit of the CMOS process that I am using).
    I wonder if there any way I can insert a controlled delay in the clock generator to compensate the phase error?

    Because this is clock generator, I assume I can't use a sample and hold to controlled delay.

    Can anyone help me?
    Thanks
    Allen

    •   Alt18th January 2018, 03:45

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    Re: How to create a controlled delay in clock generator circuit

    Start with how you mean to control the delay.

    Current starved inverters is a common delay technique.
    These need 1 or 2 bias voltages (for current mirrors).

    You might implement the same, but as a poor-boy DAC
    (a plurality of parallel inverters / TINVs, with select logic
    controlling drive strength).

    You don't want to slow edges down too much because
    that will increase jitter. You will want to resquare the
    edges at the end and maybe periodically along the chain
    if it is long.

    A Johnson counter ought to be pretty uniform with the
    exception of the carry output. Maybe you want to work
    on cleaning up the stage-stage symmetry, like putting
    dummy loads on unused but looped-forward outputs,
    or better buffering the outputs (and uniformly so), etc.



    •   Alt18th January 2018, 05:48

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    Re: How to create a controlled delay in clock generator circuit

    Thanks for your reply!
    By control the delay, I meant I want to, for example, delay one of the output clock signals by 0.1 ns, precisely.
    I am under the impression that inserting an inverter could definitely create some delay. however, such delay somewhat depends on the process variation, unmodelled parasitics, etc. Both of them will make the simulation very different from the measurement.

    And I am also curious about your comment: "Current starved inverters is a common delay technique. " Is this statement valid for clock design, which requires a relative precision?



    •   Alt18th January 2018, 07:56

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    Re: How to create a controlled delay in clock generator circuit

    Hi,

    Every good design will need specifications.
    We don't know if you are talking about 1Hz to blink a LED or 1GHz..
    Voltages, phase shift...

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. Thank you.



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    Re: How to create a controlled delay in clock generator circuit

    Hi, Thanks for the Reply.
    The input clock to the clock generator is 10GHz and the output clock I am trying to delay is at 2.5GHz. So delay about 0.1ns is kind of like 90-degree delay.



    •   Alt18th January 2018, 09:09

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    Re: How to create a controlled delay in clock generator circuit

    Quote Originally Posted by AllenD View Post
    Hi, Thanks for the Reply.
    The input clock to the clock generator is 10GHz and the output clock I am trying to delay is at 2.5GHz. So delay about 0.1ns is kind of like 90-degree delay.
    this sounds rather unrealistic. where is this 10Ghz source coming from?
    Really, I am not Sam.



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