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[SOLVED] [Synth 8-3332] Sequential element (ref_end_reg) is unused and will be removed from mo

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rafimiet

rafimiet

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I have the following code
Code VHDL - [expand]
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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/31/2017 11:13:41 AM
-- Design Name: 
-- Module Name: Refinement_Control - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Refinement_Control is
    GENERIC (N : integer := 16);
    Port ( clk : in STD_LOGIC;---Nxt = 0 means send nxt
           nxt : in STD_LOGIC_VECTOR(5 downto 0);
           en : in STD_LOGIC_VECTOR(1 downto 0);
           b0_addr : out integer range 0 TO N*N/16-1 := 0;
           b0_addr1 : out integer range 0 TO N*N/4-1 := 0;
           valid,alt : out STD_LOGIC := '0';
           ref_end : out STD_LOGIC := '0');
end Refinement_Control;
 
architecture Behavioral of Refinement_Control is
 
begin
    PROCESS(clk,en)
        variable temp_addr : integer range 0 TO N*N/16-1 := 0;
        variable addr : integer range 0 TO N*N/4-1 := 0;
        variable count,count1 : integer range 0 to 9 := 0;
    BEGIN
        if clk'event and clk = '1' then
            if en = "01" then
                if temp_addr < N*N/64 then
                    count := count + 1;
                    if count = 1 then
                        valid <= '0';
                        alt <= '0';
                    elsif count = 2 then
                        alt <= '1';
                        valid <= '1';
                    elsif count = 3 then
                        valid <= '1';
                        temp_addr := temp_addr + 1;
                        count := 0;
                    end if;
                    ref_end <= '0';
                    b0_addr <= temp_addr;
                    b0_addr1 <= temp_addr;
                elsif temp_addr < N*N/16 then
                    count := count + 1;
                    b0_addr <= temp_addr;
                    if count = 1 then
                        valid <= '0';
                        alt <= '0';
                    elsif count = 2 then
                        if count1 = 0 then
                            addr := temp_addr;
                            count := 1;
                            count1 := count1 + 1;
                        elsif count1 = 1 then
                            addr := temp_addr;
                            if nxt(5) = '0' then
                                temp_addr := temp_addr + 1;
                                count := 0;
                                count1 := 0;
                            else
                                count1 := count1 + 1;
                            end if;
                        elsif count1 = 2 then
                            addr := 4*temp_addr;
                            if nxt(4) = '0' then
                                count := 1;
                                count1 := count1 + 1;
                            else
                                count1 := count1 + 1;
                            end if;
                        elsif count1 = 3 then
                            addr := addr + 1;
                            if nxt(3) = '0' then
                                count := 1;
                                count1 := count1 + 1;
                            else
                                count1 := count1 + 1;
                            end if;
                        elsif count1 = 4 then
                            addr := addr + 1;
                            if nxt(2) = '0' then
                                count := 1;
                                count1 := count1 + 1;
                            else
                                count1 := count1 + 1;
                            end if;
                        elsif count1 = 5 then
                            addr := addr + 1;
                            if nxt(1) = '0' then
                                temp_addr := temp_addr + 1;
                                count := 0;
                                count1 := 0;
                            end if;
                        end if;
                        valid <= '0';
                        alt <= '0';
                    elsif count = 3 then
                        alt <= '1';
                        valid <= '1';
                    elsif count = 4 then
                        valid <= '1';
                        if count1 = 5 then
                            temp_addr := temp_addr + 1;
                            count := 0;
                            count1 := 0;
                        else
                            count := 1;
                        end if;
                    end if;
                    ref_end <= '0';
                    b0_addr1 <= addr;
                else
                    temp_addr := 0;
                    count := 0;
                    ref_end <= '1';
                end if;
            end if;
        end if;
    END PROCESS;
end Behavioral;

When I synthesize the code, it shows the following warning:
[Synth 8-3332] Sequential element (ref_end_reg) is unused and will be removed from module Refinement_Control.
Click to expand...
How I can rectify the issue?
 

temp_addr can never be bigger than N*N/16 so the else clause is never used and the ref_end <= '1'; can never be assigned, so temp_addr is not used and is always '0'.

Besides this I have other issues with your code. You don't seem to understand what the circuit that is generated from synthesis looks like when you use variables. Your current implementation requires an add (+1) followed by multiple comparison operations before it's registered again. Depending on the technology and the frequency you are running this at it may have issues with timing. This is one of the primary reasons I suggest that those new to VHDL should always use signals and never use variables (until you understand how they are synthesized in all use cases).

I'm not sure if the initialization on the ports: b0_addr, b0_addrl, valid, alt, and ref_end will work. I've never done this so I don't know if it is valid VHDL or causes warnings/errors at some point. I suggest you remove them.
 

ads-ee said:
temp_addr can never be bigger than N*N/16 so the else clause is never used and the ref_end <= '1'; can never be assigned, so temp_addr is not used and is always '0'.
Click to expand...
I got the point, but when I simulated the design, it was taking values greater than that...But you are right, may not be synthesizable...
ads-ee said:
Your current implementation requires an add (+1) followed by multiple comparison operations before it's registered again.
Click to expand...
Can you elaborate a bit on this? I want to understand this well...
ads-ee said:
I'm not sure if the initialization on the ports: b0_addr, b0_addrl, valid, alt, and ref_end will work. I've never done this so I don't know if it is valid VHDL or causes warnings/errors at some point. I suggest you remove them.
Click to expand...
I will take care of this in future...
 

rafimiet said:
ads-ee said:
Your current implementation requires an add (+1) followed by multiple comparison operations before it's registered again.
Click to expand...
Can you elaborate a bit on this? I want to understand this well...
Click to expand...

I wrote something about this with synthesis schematics to show the difference, but I'm not willing to search for it.
Suffice it to say a variable is evaluated and assigned immediately (not scheduled on a clock edge) therefore any logic used in the assignment ends up appearing where ever that variable is found.

e.g.
Code: 
-- this code
  out1 := a AND b;
  out2 <= out1 AND c;
-- results in this:
  out2 <= a AND b AND c;
The more logic that is assigned in the variable gets applied everywhere the variable is used.

A simple testcase will show this if you write a counter with a terminal count compare, using a variable for the counter will result in different logic being synthesized than the counter using a signal. To get the same behaviour in the counting you would also have to use a different value for the terminal count between the two implementations.

- - - Updated - - -

if temp_addr
Code: 
variable temp_addr : integer range 0 TO N*N/16-1 := 0;
is taking on values greater or equal to N*N/16 then something is going wrong with your simulator as you've defined the integer range from 0 to N*N/16-1.

Hence according to your code it is impossible for temp_addr to be >= N*N/16
Code: 
elsif temp_addr < N*N/16 then
or are you telling me that this statement isn't being evaluated properly?
 
I have a code section, where I don't understand if I can do away with variables. The functionality is as follows:
if b2 = '1' then
output1 = b1

if b2 = '0' and b1 = '0'
output1 = '0'

if b2 = '0' and b1 = '1'
output1 = ['1' sgn1]


if b4 = '1' then
output2 = b3

if b4 = '0' and b3 = '0'
output2 = '0'

if b4 = '0' and b3 = '1'
output2 = ['1' sgn1]

Final Output = Output1 & Output2
Click to expand...

The code that I wrote for this functionality involves a variable. The code is as follows
Code VHDL - [expand]
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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/31/2017 10:29:38 AM
-- Design Name: 
-- Module Name: bit_seq - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity bit_seq is
    Port ( clk,valid : in STD_LOGIC;
           b1,b2,b3,b4 : in STD_LOGIC;
           sgn1,sgn2 : in STD_LOGIC;
           BS : out STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
           n : out integer range 0 TO 7 := 0);
end bit_seq;
 
architecture Behavioral of bit_seq is
 
begin
    PROCESS(clk,valid)
        variable temp : integer range 0 TO 4 := 0;
    BEGIN
        if clk'event and clk = '1' then
            if valid = '1' then
                if b2 = '1' then
                    BS(temp) <= b1;
                    temp := temp + 1;
                elsif b1 = '0' then
                    BS(temp) <= '0';
                    temp := temp + 1;
                else
                    BS(temp) <= '1';
                    temp := temp + 1;
                    BS(temp) <= sgn1;
                    temp := temp + 1;
                end if;
                if b4 = '1' then
                    BS(temp) <= b3;
                    temp := temp + 1;
                elsif b3 = '0' then
                    BS(temp) <= '0';
                    temp := temp + 1;
                else
                    BS(temp) <= '1';
                    temp := temp + 1;
                    BS(temp) <= sgn2;
                    temp := temp + 1;
                end if;
                n <= temp;
                BS(8 downto 4) <= (OTHERS => '0');
            else
                n <= 0;
                BS(8 downto 0) <= (OTHERS => '0');
            end if;
            temp := 0;
        end if;
    END PROCESS;
end Behavioral;

Can I do away with this variable here? Or it is OK to use it?
 

ads-ee said:
I'm not sure if the initialization on the ports: b0_addr, b0_addrl, valid, alt, and ref_end will work. I've never done this so I don't know if it is valid VHDL or causes warnings/errors at some point. I suggest you remove them.
Click to expand...

It is valid VHDL but it should be avoided for output ports.
It must be used for input ports that are allowed to be left unconnected.
For output ports, it is the value used before the first assignment (otherwise it is U in simulation).

Simulation, all output ports:
==================
It always works, but why use it?

Synthesis, combinatorial output ports:
============================
It has no effect

Synthesis, registered output ports:
==========================
It doesn't work for all architectures.
Ok for most (all?) Xilinx and Altera FPGA's.
It doesn't work for ASIC's and Actel ProASIC FPGA's.
 
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