rafimiet
Member level 5
I have the following code
When I synthesize the code, it shows the following warning:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10/31/2017 11:13:41 AM -- Design Name: -- Module Name: Refinement_Control - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Refinement_Control is GENERIC (N : integer := 16); Port ( clk : in STD_LOGIC;---Nxt = 0 means send nxt nxt : in STD_LOGIC_VECTOR(5 downto 0); en : in STD_LOGIC_VECTOR(1 downto 0); b0_addr : out integer range 0 TO N*N/16-1 := 0; b0_addr1 : out integer range 0 TO N*N/4-1 := 0; valid,alt : out STD_LOGIC := '0'; ref_end : out STD_LOGIC := '0'); end Refinement_Control; architecture Behavioral of Refinement_Control is begin PROCESS(clk,en) variable temp_addr : integer range 0 TO N*N/16-1 := 0; variable addr : integer range 0 TO N*N/4-1 := 0; variable count,count1 : integer range 0 to 9 := 0; BEGIN if clk'event and clk = '1' then if en = "01" then if temp_addr < N*N/64 then count := count + 1; if count = 1 then valid <= '0'; alt <= '0'; elsif count = 2 then alt <= '1'; valid <= '1'; elsif count = 3 then valid <= '1'; temp_addr := temp_addr + 1; count := 0; end if; ref_end <= '0'; b0_addr <= temp_addr; b0_addr1 <= temp_addr; elsif temp_addr < N*N/16 then count := count + 1; b0_addr <= temp_addr; if count = 1 then valid <= '0'; alt <= '0'; elsif count = 2 then if count1 = 0 then addr := temp_addr; count := 1; count1 := count1 + 1; elsif count1 = 1 then addr := temp_addr; if nxt(5) = '0' then temp_addr := temp_addr + 1; count := 0; count1 := 0; else count1 := count1 + 1; end if; elsif count1 = 2 then addr := 4*temp_addr; if nxt(4) = '0' then count := 1; count1 := count1 + 1; else count1 := count1 + 1; end if; elsif count1 = 3 then addr := addr + 1; if nxt(3) = '0' then count := 1; count1 := count1 + 1; else count1 := count1 + 1; end if; elsif count1 = 4 then addr := addr + 1; if nxt(2) = '0' then count := 1; count1 := count1 + 1; else count1 := count1 + 1; end if; elsif count1 = 5 then addr := addr + 1; if nxt(1) = '0' then temp_addr := temp_addr + 1; count := 0; count1 := 0; end if; end if; valid <= '0'; alt <= '0'; elsif count = 3 then alt <= '1'; valid <= '1'; elsif count = 4 then valid <= '1'; if count1 = 5 then temp_addr := temp_addr + 1; count := 0; count1 := 0; else count := 1; end if; end if; ref_end <= '0'; b0_addr1 <= addr; else temp_addr := 0; count := 0; ref_end <= '1'; end if; end if; end if; END PROCESS; end Behavioral;
When I synthesize the code, it shows the following warning:
How I can rectify the issue?[Synth 8-3332] Sequential element (ref_end_reg) is unused and will be removed from module Refinement_Control.