Derun93
Member level 3
Hi everyone,
I am having a problem with accumulator code in Verilog. I simply generate pseudo random signals. Then, change the random signal level -1 to 1 from 0 to 1 so it is signed. Later, obtained 'acmin'. In this point, I need to accumulate 'acmin' signals. Debugger doesn't give me any error but I can't see any result. Can you help me to find problem?
Thanks.
Derun.
I am having a problem with accumulator code in Verilog. I simply generate pseudo random signals. Then, change the random signal level -1 to 1 from 0 to 1 so it is signed. Later, obtained 'acmin'. In this point, I need to accumulate 'acmin' signals. Debugger doesn't give me any error but I can't see any result. Can you help me to find problem?
Thanks.
Derun.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 module lfsr(clk, rst, seed, load, R, acc); input [3:0] R; input [26:0] seed; input load; input rst; input clk; reg [3:0]q; wire [3:0] S; wire overflow; wire [3:0] acmin ; wire [26:0] state_out; wire [26:0] state_in; output [7:0] acc; reg [7:0] acc; flipflop F[26:0] (state_out, clk, rst, state_in); mux M1[26:0] (state_in, load, seed, {state_out[25],state_out[24],state_out[23],state_out[22],state_out[21],state_out[20],state_out[19],state_out[18],state_out[17],state_out[16],state_out[15],state_out[14],state_out[13],state_out[12],state_out[11],state_out[10],state_out[9],state_out[8],state_out[7],state_out[6],state_out[5],state_out[4],state_out[3],state_out[2], state_out[1], state_out[0], nextbit}); xor G1(nextbit, state_out[5], state_out[2], state_out[1], state_out[26]); // Pseudorandom generator always@(clk) begin if (state_out[26]==0) q=4'b1111; // 0 to -1 else q=4'b0001; //1 to 1 end assign acmin= R*q; // accumulator input always@(clk) begin if(rst) acc = 8'b00000000; else acc = acc + acmin; end endmodule