+ Post New Thread
Results 1 to 5 of 5
  1. #1
    Advanced Member level 2
    Points: 3,910, Level: 14

    Join Date
    Apr 2011
    Posts
    540
    Helped
    24 / 24
    Points
    3,910
    Level
    14

    VHDL: How to create type for unconstrained array for entity port

    Here is the entity:

    Code:
    entity col_piso_sr is
    	generic (
    		word_len: natural := 8
    	);
    	port (
    		p_in_7: in std_logic_vector(word_len-1 downto 0);
    		p_in_6: in std_logic_vector(word_len-1 downto 0);
    		p_in_5: in std_logic_vector(word_len-1 downto 0);
    		p_in_4: in std_logic_vector(word_len-1 downto 0);
    		p_in_3: in std_logic_vector(word_len-1 downto 0);
    		p_in_2: in std_logic_vector(word_len-1 downto 0);
    		p_in_1: in std_logic_vector(word_len-1 downto 0);
    		p_in_0: in std_logic_vector(word_len-1 downto 0);
    
    		s_out: out std_logic_vector(word_len-1 downto 0);
    		
    		p_in_e: in std_logic;
    		s_out_e: in std_logic;
    
    		clk: in std_logic;
    		reset_n: std_logic
    	);
    end entity;
    I am sure that there is a way to create a type in a packge that is an array and then declare the p_in_# signals in a single line in the entity. This will further simplify the architecture RTL coding. Since the word_len is a generic here and not found inside the package itself, how does one go about doing this?

    - - - Updated - - -

    The array p_in_t will be (7 downto 0) of std_logic_vector that is uncontrained. This is what is making it confusing. The inner dimension of the array is uncontrained rather than the outer one.

    •   Alt12th January 2018, 14:08

      advertising

        
       

  2. #2
    Advanced Member level 4
    Points: 7,331, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,079
    Helped
    238 / 238
    Points
    7,331
    Level
    20
    Blog Entries
    1

    Re: VHDL: How to create type for unconstrained array for entity port

    type c_8b_8d_array is array (0 to 7) of std_logic_vector(word_len-1 downto 0);

    p_in_t : in c_8b_8d_array;


    p_in_t(0) --- p_in_0
    .
    .
    p_in_t(7) --- p_in_7
    .....yes, I do this for fun!



    •   Alt12th January 2018, 14:19

      advertising

        
       

  3. #3
    Advanced Member level 2
    Points: 3,910, Level: 14

    Join Date
    Apr 2011
    Posts
    540
    Helped
    24 / 24
    Points
    3,910
    Level
    14

    Re: VHDL: How to create type for unconstrained array for entity port

    Yes, but where to declare the type? In a package? If I declare it in a package then how to make the generic called word_len to reach the package so the inner dimension of the p_in_t can be constrained ?



    •   Alt12th January 2018, 14:23

      advertising

        
       

  4. #4
    Advanced Member level 4
    Points: 7,331, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,079
    Helped
    238 / 238
    Points
    7,331
    Level
    20
    Blog Entries
    1

    Re: VHDL: How to create type for unconstrained array for entity port

    I declare it in a separate file named vhdl_pkg.vhd

    Then the entity block which needs is...

    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use work.vhdl_pkg.all;
    library unisim;
    use unisim.vcomponents.all;
    
    entity my_entity_top is
        generic(
    .
    .
    .
    .....yes, I do this for fun!



  5. #5
    Advanced Member level 5
    Points: 35,892, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,567
    Helped
    1914 / 1914
    Points
    35,892
    Level
    46

    Re: VHDL: How to create type for unconstrained array for entity port

    You cannot do this with VHDL '93, as types need to constrained in all dimensions other than the highest, so you are limited to declaring the constant and type in a package, and you cannot use a generic for the word width, like dpaul has demostrated

    VHDL 2008, on the other hand, allows ALL dimensions to be unconstrained (should be supported by everyone now), and even allows you to have a type as a generic (will work in simulation, doubtfull for synthesis)/

    so, for what you want to do:

    Code VHDL - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    
    -- ... in a package:
    type slv_array_t is array(natural range <>) of std_logic_vector;
     
    -- .. on your entity
    generic(
      N : natural;
      WW : natural
    )
    port (
      input  : in slv_array_t(0 to N-1)(WW-1 downto 0)
    );


    1 members found this post helpful.

--[[ ]]--