amvrao
Newbie level 2
We are using clocking blocks in systemverilog. we are seeing some weird behaviour when we are waiting on clocking block input signal
We wait for the input of clocking block signal to change to '1', then wait for one clock and then read some signal. But when we wait for one clocking block, one clock delay is not seen.
Output:
We wait for the input of clocking block signal to change to '1', then wait for one clock and then read some signal. But when we wait for one clocking block, one clock delay is not seen.
Code:
interface tif(input clk);
logic data;
clocking cb@(posedge clk);
input data;
endclocking
endinterface
module test;
reg clk;
tif tif1(clk);
initial begin
tif1.data = 1'b0;
#12;
tif1.data <= 1'b1;
end
initial begin
[COLOR="#FF0000"] wait(tif1.cb.data == 1'b1); //This happens on 15ns. (12ns assignment. 15ns on posedge of clock)
$display("[%t]:: After waiting for cb.data",$time); //Here time is 15ns.
@(tif1.cb); //Expect this to happen at next clock edge
$display("[%t]:: After waiting for cb",$time); //Here time is 15ns. //expect the time here to be 25ns. one posedge later.[/COLOR]
end
initial
begin
#1000 $finish;
end
initial
begin
clk <= 1'b0;
forever
begin
#5;
clk <= ~clk;
end
end
endmoduleOutput:
Code:
[ 15]:: After waiting for cb.data
[ 15]:: After waiting for cb //Here we are waiting for @(tif1.cb), but this is happening on same clock