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    Wait on clocking block input signals

    We are using clocking blocks in systemverilog. we are seeing some weird behaviour when we are waiting on clocking block input signal
    We wait for the input of clocking block signal to change to '1', then wait for one clock and then read some signal. But when we wait for one clocking block, one clock delay is not seen.

    Code:
    interface tif(input clk);
    
    logic data;
    
    clocking cb@(posedge clk);
    input data;
    
    endclocking
    
    endinterface
    
    module test;
    
    reg clk;
    tif tif1(clk);
    
    initial begin
        tif1.data = 1'b0;
        #12;
        tif1.data <= 1'b1;
    end
    
    initial begin
        wait(tif1.cb.data == 1'b1);  //This happens on 15ns. (12ns assignment. 15ns on posedge of clock)
        $display("[%t]:: After waiting for cb.data",$time); //Here time is 15ns.
        @(tif1.cb); //Expect this to happen at next clock edge
        $display("[%t]:: After waiting for cb",$time); //Here time is 15ns. //expect the time here to be 25ns. one posedge later.
    end
    
    initial
    begin
    #1000 $finish;
    end
    initial
    begin
        clk <= 1'b0;
        forever
        begin
            #5;
            clk <= ~clk;
        end
    end
    endmodule

    Output:
    Code:
    [                  15]:: After waiting for cb.data
    [                  15]:: After waiting for cb    //Here we are waiting for @(tif1.cb), but this is happening on same clock

    •   Alt12th January 2018, 12:48

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  2. #2
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    Re: Wait on clocking block input signals

    The problem here is that clocking block inputs are synchronous events with the clocking block event. Instead of the wait statement use

    Code Verilog - [expand]
    1
    
    @(tif1.cb iff tif1.cb.data)
    My general rule is do not mix clocking block events with any other events or wait statements.

    BTW, another general rule is only use blocking assignments for generating clocks. This is especially important when you are generating multiple clocks that are derivatives of other clocks.
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation


    1 members found this post helpful.

    •   Alt13th January 2018, 17:40

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  3. #3
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    Re: Wait on clocking block input signals

    Quote Originally Posted by dave_59 View Post
    The problem here is that clocking block inputs are synchronous events with the clocking block event. Instead of the wait statement use

    Code Verilog - [expand]
    1
    
    @(tif1.cb iff tif1.cb.data)
    My general rule is do not mix clocking block events with any other events or wait statements.

    BTW, another general rule is only use blocking assignments for generating clocks. This is especially important when you are generating multiple clocks that are derivatives of other clocks.
    Thanks dave for input. this is new information that i knew we can use iff inside a @ event.

    The same code provides different output when run on questa simulator: (The original code i posted)
    # [ 15]:: After waiting for cb.data
    # [ 25]:: After waiting for cb



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