Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

90nm calibre LVS error

Status
Not open for further replies.
A

Alipoursaadaty

Member level 3
Joined
Dec 4, 2015
Messages
60
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
13,625
Hi guys
I drew an LNA layout. I got DRC with *.DN.* and CSR.* error & ignored them.
But now, when i want to take LVS, i get "Source could not be raed" error as shown in the picture that it has attached to this message.
You can see input option settings in the second picture i attached.
How can i resolve it???
please help me
Untitled.jpgUntitled2.jpg
 

A distinct error message, I'd say. Try & find the "RPPOLYWO" SUBCKT in the given filename. If it's not there (probably), then check where this SUBCKT lives (analoglib ?) and add the appropriate filename to your Inputs setup.
 

erikl said:
A distinct error message, I'd say. Try & find the "RPPOLYWO" SUBCKT in the given filename. If it's not there (probably), then check where this SUBCKT lives (analoglib ?) and add the appropriate filename to your Inputs setup.
Click to expand...

Thank you for replying.
But i get this error. It says not compared.
Is this error for LVS option settings???
Untitled.jpg
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top