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    Can one force ModelSim to flag signals with multiple drivers?

    Signals that have multiple drivers (by mistake of course) may look fine in simulation sometimes and become X at other times. When one tries to synthesize the code, it will always be flagged up as such code cannot be synthesized. Anyway, is there a way to force ModelSim to flag such signals when it is compiling the code so we can remove the mistake?

    •   Alt11th January 2018, 22:23

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    Re: Can one force ModelSim to flag signals with multiple drivers?

    The simple answer is: run synthesis before you simulate.



    •   Alt11th January 2018, 23:22

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    Re: Can one force ModelSim to flag signals with multiple drivers?

    use std_ulogic and std_ulogic_vector instead of std_logic and std_logic_vector. These are unresolved types and it is a error to have multiple drivers.
    Otherwise a simulation with a good testbench should catch it. And finally, the synth should get it pretty quick.


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    •   Alt11th January 2018, 23:48

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    Re: Can one force ModelSim to flag signals with multiple drivers?

    Its just that the synthesis tool from Altera (now Intel) takes so much longer than ModelSim to do its job



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    Re: Can one force ModelSim to flag signals with multiple drivers?

    You probably can write a TCL script based on getting the nets and using the drivers function on them and then whatever counts list size in TCL. I'm fairly sure there is a way to do this, I don't know if it is built into modelsim as an efficient command though.



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