Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[Moved]: Can MOS transistor put close to NT_N layer??

Status
Not open for further replies.
N

NovelPanda

Junior Member level 3
Joined
Apr 1, 2017
Messages
29
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
281
Dear all:

I want to put NT_N layer between two blocks to isolate their mutual noise coupling. NT_N is an layer in which neither N or P will be doped: it is an intrinsic silicon region with high resistivity. However, if NT_N is too closed to MOS transistor, would the MOS be malfunction or affected? Assume that the MOS has been enclosed by p-substrate ring or deep N-well (triple well).

Thanks in advanced!
 

Re: Can MOS transistor put closed to NT_N layer??

Need to specify your foundry and process please.
 

Re: Can MOS transistor put closed to NT_N layer??

It is TSMC 40nm RF-CMOS process~
 

NovelPanda said:
NT_N is an layer in which neither N or P will be doped: it is an intrinsic silicon region with high resistivity. However, if NT_N is too closed to MOS transistor, would the MOS be malfunction or affected? Assume that the MOS has been enclosed by p-substrate ring or deep N-well (triple well).
Click to expand...
A min. spacing will be necessary (as there's no abrupt transition from intrinsic to highly doped silicon).
The DRC will tell you.
 

Thank you! Actually the spacing requirement is always fulfilled and there is no such error in DRC. My concern is that I put NT_N too closed to the core circuit and the post-layout simulation fails to capture the influences..
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top